Video Roundup 
Sanjay Gangal
A showcase for electronic design videos around the world-wide web. Manufacturing Closure for Advanced Node Designs within Place and RouteFebruary 8th, 2012 by Sanjay Gangal
Mentor Graphics developed Calibre InRoute to support manufacturing closure for advanced node designs by bringing Calibre signoff capabilities into the place and route environment. This short video provides an overview of the Calibre InRoute solution.
Computational Lithography Solutions for 22nm and BeyondFebruary 7th, 2012 by Sanjay Gangal
Mentor Graphics is committed to being the leader in computational lithography solutions for 22nm and beyond. This video presentation discusses the challenges and necessary solutions for IC success.
Tutorial: Better PCB Power Design with DC Drop AnalysisFebruary 6th, 2012 by Sanjay Gangal
DC Drop Analysis is a crucial step in any PCB design flow. Learn how utilizing DC Drop Analysis can greatly enhance your ability to identify potential power issues. Explore how co-simulating DC Drop and Thermal Analyses can optimize your entire power delivery network. Presented by Steve McKinney of Mentor Graphics
Accelerating Schematic Driven Layout of Analog ICsFebruary 3rd, 2012 by Sanjay Gangal
A demonstration of how Schematic Driven Layout (SDL) is used in Tanner’s L-Edit using HiPer DevGen for analog layout acceleration.
Creating Differentiated Technology in SiliconFebruary 2nd, 2012 by Sanjay Gangal
Rajeev Madhavan, Magma CEO, describes how Magma’s Silicon One initiative provides advanced digital implementation, analog/mixed-signal design, timing analysis, circuit simulation and yield management technology solutions that allow semiconductor companies to develop differentiated and profitable SoCs, ASICs, memory devices, analog designs and high-performance cores.
Accelerating Mixed-Signal Design for Low Power using TitanFebruary 1st, 2012 by Sanjay Gangal
Mar Hershenson, Vice President, Product Development, Custom Design Business Unit at Magma, provides an overview of Titan and how it allows analog designers to more fully explore the design space to significantly improve performance and dramatically reduce power consumption on both new and existing analog designs.
Accelerating Analog IC Layout with Current MirrorsJanuary 30th, 2012 by Sanjay Gangal
This is a demonstration of using current mirrors in Tanner EDA’s HiPer DevGen analog layout acceleration tool.
Tutorial: Power Management Cells in Low Power DesignJanuary 27th, 2012 by Sanjay Gangal
Josefina Hobbs, Technical Solutions Architect for the Synopsys Eclypse Low Power Solution, describes the various special cells that can be used in UPF-enabled advanced low power design.
Synopsys USB 3.0 Host and PHY Interop with USB Devices of All SpeedsJanuary 26th, 2012 by Sanjay Gangal
Eric Huang demonstrates USB 3.0 interoperability with a USB 3.0 Certification Gold Tree including all USB traffic types.
Cool Things You Can Do With the Discovery Visualization Environment (DVE) — Searching And Cool GUI TipsJanuary 25th, 2012 by Sanjay Gangal
Verification expert Yaron Ilani explains how to easily search for signals or scopes in the Discovery Visualization Environment (DVE) and gives some great GUI tricks.
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