Verific Celebrates 20 years in the SystemVerilog and VHDL Parser Business

Sanjay Gangal interviewed Michiel Ligthart, President and COO at Verific Design Automation at the 2019 DVCon.

SG: Thank you very much for coming over here. I heard Verific had a 20 year anniversary.

ML: That’s correct. A couple of weeks ago, on January 31st, we celebrated Verific Design Automation’s 20th anniversary. In 1999, Rob Dekker – our founder and CTO, started the company. So, we celebrated with all the US West Coast employees and their families, and had a small party. Our Indian colleagues in the Kolkata office are going to have a similar celebration in a couple of weeks. So, it’s great fun.

SG: That’s awesome. Tell us about how did you guys get started? Give us a little bit of your startup magic.

ML: So, let’s try to keep this brief. Rob Dekker, and I were both working at Exemplar Logic for a long time, and Exemplar was acquired by Mentor Graphics. We both stuck around for a little bit longer, a year or two I think – and then we left around the same time. I did something completely different in asynchronous technology, and Rob started Verific Design Automation. Initially his ideas were to do something in verification, but that didn’t exactly pan out, as we now all know. Because he started out with building a Verilog parser, and as soon as he had that one written, several people that knew him from the past said, “Hey, we would like to license that from you, and use it for our own EDA tools.”

ML: And he thought, “Well that’s a good idea to pay the bills.”. So, he started doing that, and that’s how it all started… Initially with a few customers, who basically pulled the software from underneath him. He continued that business model first by himself; then with the first employee, Lawrence Neukom, who is still with us. Lawrence took a sabbatical for two years to travel around Europe. But, he came back, and is now one of our senior engineers still working on projects, like the UPF analyzer. And things were going so well that a few years later, when my sidetrack in the asynchronous logic startup didn’t work out so well; actually – it failed, Rob asked me to join him.

ML: And that is how I joined 15 years ago. We have clearly expanded the company to become a force of nature inside the EDA and semiconductor industry. At some point we got the Indian office, which was headed by Abhijit Chakrabarty, who we also knew from our Exemplar days. We got Hoa Dinh, the customer support manager. Most of our customers know him well, because he’s the first line of defense when they email us. And he joined us now, I think, 14 years ago. So, we built a great little company. At the moment – we have 66 paying, active licensees worldwide. They are from the larger EDA companies, to the smaller EDA startups.All the FPGA companies are using us. And a plethora of semiconductor companies that have internal flows, and internal design tools, they have all capitalized on Verific as well.

ML: All the FPGA companies are using us. And plethora of semiconductor companies that have internal flows, and internal design tools, they have all capitalized on Verific as well.

SG: Would it be incorrect to say that more than 70, 80%, maybe 90% of the people using many of these tools in the EDA industry- the chip designers and system designers, that they may or may not know, that underlying technology is yours?

ML: Absolutely, they may or may not know. And that’s one of the reasons why we like to come to DVCON, because there we do talk more to the design engineers and the verification engineers- the end users. And then I give them examples. I say, “Hey! do you use this tool?” And they say “Yes.” I say “Well, that is the front-end… The SystemVerilog front-end from Verific, or a VHDL front-end.” And they’re always pleased, and say, “Oh, that’s nice to know.”

SG: What are all the different parsers that you have under your belt now?

ML: It’s the System Verilog parser, it’s our VHDL parser, and we have a UPF parser. And all parsers of course also come with elaborators, either static elaboration, or RTL elaboration. We have a few side parsers. We also take care of the Liberty format, the Synopsys style library. There’s an EDIF parser from the old days, and there’s still people that are using those. The AMS extension for Verilog is supported. And I think that’s about it.

SG: Let me go back a little bit just for a second. Were you guys always self-funded, or did you get investors involved also?

ML: No, we were very fortunate that we did not need outside investors. Rob started on his own, and over the years we have been able to just grow by ourselves, without external investment.

SG: Part of the fun, being not having any external funding, is there is no pressure to exit as well.

ML: That’s correct, we are not beholden to anyone. And I don’t think that we will be looking for an exit strategy any time soon, because we have a great little company going on. We are very well respected by our customers, and we like it like that.

SG: How long do you think you can keep on going like this, or you think there’s an exit at some point?

ML: I really am not sure when that will be. Of course, there will come a time that elder people in the organization may say, “Well, I want to work a little bit less.” At the moment we’re still in our mid 50s, so we can keep going on for a while longer. And our colleagues in the India office, they’re about 10 years younger than we are. So, the industry does not have to be afraid that we suddenly will disappear.

SG: You don’t think somebody like Mentor, now Siemens, or Cadence, Synopsys, somebody is not going to come along and say, “Oh, we just want to acquire you and eat all of you?”

ML: If they would like to, they know where to find me! michiel@verific.com.

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