This is a demonstration of manipulating differential pairs in Tanner EDA’s HiPer DevGen analog layout acceleration tool.
Video Roundup
Archive for February, 2012
Accelerating Analog IC Layout with Differential Pairs
Friday, February 17th, 2012DesignCon 2012: Joint ANSYS / Apache Interview on Product Roadmap and Integration
Tuesday, February 14th, 2012The worldwide need for smart, energy-efficient electronics has never been greater while engineering challenges continually expand. Solutions to these engineering challenges rely on accurate, predictive simulation software. The acquisition of Apache complements ANSYS’ software solutions by bringing together best-in-class products that drive ANSYS’ system vision for integrated circuits, electronic packages and printed circuit boards.
Aveek Sarkar from Apache and Larry Williams of ANSYS discuss product roadmaps and integration from both companies.
DesignCon 2012: New HyperLynx Release 8.2 with Thermal / Power Co-simulation Analysis
Monday, February 13th, 2012Steven McKinney from Mentor Graphics gave an update on the new HyperLynx Release 8.2 with thermal / power co-simulation analysis at DesignCon 2012.
Steven is a business development manager for Mentor Graphic’s Board System Division where he supports Mentor’s PCB analysis technologies which include tools for Signal Integrity, Power Integrity, Thermal and EMC design. Steven has previously held roles in technical marketing at Mentor Graphics, specializing in signal integrity and EMC analysis tools and educating the engineering community on signal integrity, power integrity, and EMC design issues. Prior to working for Mentor, Steven was a signal integrity engineer at Dell Computer developing server hardware. Steven received his BSEE and MSEE from North Carolina State University.
Calibre InRoute: Signoff Metal Fill Insertion, CMP Impact and Olympus Timing Analysis
Friday, February 10th, 2012This presentation is by Benny Winefeld, Product Engineering Manager, Place and Route Division at Mentor Graphics. By using Calibre InRoute, the effects of metal fill insertion and CMP on routing and signal timing can be analyzed for a physical design from within the Olympus environment.
Calibre InRoute – Signoff Litho (LFD) Analysis and Automated Repair
Thursday, February 9th, 2012This presentation is by Benny Winefeld, Product Engineering Manager, Place and Route Division at Mentor Graphics. By using Calibre InRoute, sign-off lithography (LFD) analysis and automatic repair can be done for a physical design from within the Olympus environment.
Manufacturing Closure for Advanced Node Designs within Place and Route
Wednesday, February 8th, 2012Mentor Graphics developed Calibre InRoute to support manufacturing closure for advanced node designs by bringing Calibre signoff capabilities into the place and route environment.
This short video provides an overview of the Calibre InRoute solution.
Computational Lithography Solutions for 22nm and Beyond
Tuesday, February 7th, 2012Mentor Graphics is committed to being the leader in computational lithography solutions for 22nm and beyond. This video presentation discusses the challenges and necessary solutions for IC success.
Tutorial: Better PCB Power Design with DC Drop Analysis
Monday, February 6th, 2012DC Drop Analysis is a crucial step in any PCB design flow. Learn how utilizing DC Drop Analysis can greatly enhance your ability to identify potential power issues. Explore how co-simulating DC Drop and Thermal Analyses can optimize your entire power delivery network.
Presented by Steve McKinney of Mentor Graphics
Accelerating Schematic Driven Layout of Analog ICs
Friday, February 3rd, 2012A demonstration of how Schematic Driven Layout (SDL) is used in Tanner’s L-Edit using HiPer DevGen for analog layout acceleration.
Creating Differentiated Technology in Silicon
Thursday, February 2nd, 2012Rajeev Madhavan, Magma CEO, describes how Magma’s Silicon One initiative provides advanced digital implementation, analog/mixed-signal design, timing analysis, circuit simulation and yield management technology solutions that allow semiconductor companies to develop differentiated and profitable SoCs, ASICs, memory devices, analog designs and high-performance cores.
