Posts Tagged ‘EDA’
Monday, December 30th, 2013
Please allow me to start this post with a sincere wish for all of our readers to have a happy and healthy holiday season. There are many enjoyable activities both sacred and secular this time of year, something for everyone whatever your personal beliefs. I hope that you all have the chance to relax a bit and share some delicious food with family and friends.
I thought about writing a column on the top 5 holiday wishes for verification engineers, but I felt that it would be a bit presumptuous to speak for you. We do work very hard to understand what you need in order to tailor our products to gaps in your verification process and speed up your project. Therefore, I’m going to offer 5 gifts for you, the verification engineer, that are available with Breker’s products. I hope that you like them!
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Tags: applications, Breker, EDA, emulation, functional verification, graph, production software, reuse, scenario model, simulation, SoC verification, system coverage, test generation, TrekSoC, TrekSoC-Si, use cases, uvm, verification IP, VIP
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Tuesday, December 10th, 2013
As you likely know by now, Breker’s primary focus is on verifying SoCs with one or more embedded processors. Sometimes these processors are homogenous, most commonly either the Intel/AMD x86 or ARM architecture. Other SoCs have multiple heterogeneous processors, possibly a diverse mix of cores from x86, ARM, MIPS, ARC, Tensilica, etc.
The trade press devotes a lot of virtual ink to covering the “war” for embedded processor dominance. An article last week made the case for ARM winning. A recent white paper discussed “heterogeneous multi-processing” using ARM’s “big.LITTLE” approach of multiple cores with the same architecture but different performance characteristics. Another article reminded us not to forget about DSPs in the heterogeneous mix. The same could be written about GPUs. So what is Breker’s take on all this?
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Tags: AMD, ARC, ARM, Breker, DSP, EDA, functional verification, GPUs, Intel, IP, Synopsys, Tensilica, verification IP, x86
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Wednesday, December 4th, 2013
As I hoped, my recent post challenging Jasper Design Automation’s statement that “formal will dominate verification” has drawn very good readership and generated some stimulating industry discussions. Today, Joe Hupcey III from Jasper responds and offers more ammunition for their claims of dramatic recent advances in the power and usability of formal technology:
Thanks to the folks at Breker for the comments and analysis in your post asking “Will Formal Really Dominate Verification?” in reference to Jasper’s recent assertion of formal’s ascendancy. As your thoughtful post acknowledges, verifiers are seeing formal starting to take over block and unit level verification, as well as select system-level applications. Indeed, the industry has seen this movie twice before – specifically, the growth of emulation into the mainstream and again with constrained-random simulation.
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Tags: Breker, constrained-random, EDA, formal analysis, formal apps, jasper, Moore's Law, simulation, SoC verification, uvm
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Tuesday, November 26th, 2013
The Breker Trekker has been publishing for about seven months now, with 32 posts to date, so running just about once a week. When we started, we committed a new post every two weeks so we’ve been running well ahead of our own expectations. We’re very happy with the growth of our readership and we’d like to take this chance to thank every one of you reading this.
Frankly, we have not been as successful at driving an ongoing dialogue via comments. We’ve had a few comments here and there but not nearly as many as we would like to see. So for this week’s post we’re trying something different: posing a question directly to our readers and heartily encouraging all of you to share your thoughts by leaving a comment at the bottom. Today’s topic: which conferences and trade shows do you find most useful?
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Tags: arrm techcon, Cadence, CDNLive, conference, dac, dvcon, EDA, functional verification, SNUG, Synopsys
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Monday, October 28th, 2013
Over the last couple of decades, vendor-specific conferences have complemented and in some markets even supplanted general industry events. Intel, Microsoft, Sun/Oracle, Apple, and many other companies have had huge, successful shows year after year. Perhaps it’s a sign of a certain level of maturity when a company has the resources to hold its own event and the appeal to attract a large crowd.
In the world of EDA (and IP, and embedded systems), ARM is certainly one of the biggest recent success stories. As the company has grown, its small technical events have evolved into a major show now known as ARM TechCon. Breker will be both speaking and exhibiting at this week’s event in Santa Clara, just down the road from Breker’s headquarters in San Jose.
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Tags: ARM TechCon, Breker, EDA, functional verification, SoC verification, TrekSoC, TrekSoC-Si
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Tuesday, October 15th, 2013
All of us at Breker are excited as we write this post, since we’ve just made our most important product announcement in several years. We’ve expanded the Breker product line by adding TrekSoC-Si, a brand-new tool that generates multi-threaded, multi-processor, self-verifying C test cases for in-circuit emulation (ICE), FPGA-based prototypes, and actual production silicon. In other words, TrekSoC-Si does for hardware platforms what TrekSoC did for simulation.
We’ll talk more about how TrekSoC-Si works in a moment. But first it’s important to note that both TrekSoC and TrekSoC-Si use the same graph-based scenario models as input to describe the intended behavior of the SoC and provide a test plan. This means that, for the first time in the industry, you can achieve horizontal verification reuse across your entire project schedule, from high-level simulation models all the way through your first chips arriving from the foundry.
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Tags: Breker, EDA, functional verification, graph, reuse, scenario model, SoC verification, Trek, TrekSoC, TrekSoC-Si, verification IP, VIP
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Tuesday, September 24th, 2013
I had planned to write today about the TrekBox module, an essential part of TrekSoC that links the code running in the embedded processors with the I/O pins of an SoC. But, in the course of reviewing my various daily news digests, I read the curiously titled blog post “Tightlipped Unicorns & Monochrome Rainbows” on the Electronic Engineering Times site. It moved my thoughts in other directions entirely, so here is the result.
In the post, Radfan CTO Simon Barker argues that startups should be more honest about the challenges they face in order to obtain help or advice from those who’ve already lived through such adventures. He maintains that company founders who automatically say “Great!” when asked how things are going are missing an opportunity to garner such assistance and are wasting their time at startup events. This position triggered three major lines of thought for me.
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Tags: accountability group, advisers, austin, Breker, EDA, functional verification, startup
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Tuesday, September 17th, 2013
A notice about “early bird” registration for the 11th International System-on-Chip (SoC) Conference, Exhibit, and Workshops arrived in my inbox late last week. It reminded me that this event is coming up quickly (October 23-24) and that, among other things, I’d better get my slides done in time to make it into the Proceedings. My talk is called “The Search for a Truly Unified Verification Methodology” and it will be on the second day at 4:05pm.
If you look at the program, you’ll quickly see that this is one of the most diverse conferences of the year. A wide variety of experts from both academia and the commercial world considers SOC development from many different angles. One minute you may be listening to a talk on high-level system performance measurement, and the next on the silicon structures for a new type of on-chip memory array.
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Tags: Breker, EDA, functional verification, Irvine, SoC Conference, SoC verification, verification methodology
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Tuesday, September 3rd, 2013
In just a week, my last post has become the most-read since we launched The Breker Trekker blog. That’s fine with me; beneath the intentionally provocative title I had some serious observations on how the EDA industry has evolved over the last couple of decades. My thought for the week is “never underestimate the power of zombies to grab people’s interest.” Mentioning zombies make me think of vampires, since the two are so intertwined in popular culture. There are lots of articles on why we’re so fascinated with these two creatures, and what it means when one is more popular than the other.
I’ll bet that most of you are running ahead of me now and thinking, “Vampires? This must be Breker’s column about venture capitalists.” Indeed this is a post about investors and their role in the formation and fate of EDA companies. Sure, some venture capitalists (VCs) might be viewed as vampires or vultures. But in my personal experience I’ve seen a wide range of investors with very different motivations and methods of interacting with their startups, most of them quite positive.
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Tags: Breker, EDA, functional verification, funding, investors, SoC verification, VC, venture capitol
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Tuesday, August 27th, 2013
From the blog stats it seems clear that late August is a slow time with lots of folks on vacation, so I’ll take a break from the heavy technical topics to chat about the industry. Long before I worked for an EDA company, I was an active participant as a user of EDA tools and as a CAD manager tasked with evaluating them and integrating them together. In that role, I loved working with interesting startups that had new ideas for electronic development.
It was part of my job to follow the EDA industry closely so that we could choose our tool investments based on both strength of technology and likelihood of vendor success. It seemed to me that the industry was divided into only three categories: major leaguers, minor leaguers, and startups. I observed that nearly all EDA startups disappeared after three or four years, with three possible endgames: acquisition, initial public offering (IPO), or bankruptcy.
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Tags: avant, behemoth, Breker, Cadence, corner store, EDA, functional verification, jasper, major leaguer, mentor, minor leaguer, SoC verification, startup, Synopsys
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