Posts Tagged ‘Breker’
Tuesday, February 11th, 2014
For today’s blog post, we use as our text a recent article on SemiWiki by well-known verification expert Hemendra Talesara. He provides a nice summary of a recent talk given in Austin by another verification expert, Harry Foster from Mentor. Many of you have probably seen Harry’s blog posts dissecting in great detail the results of a bi-annual survey that Mentor commissions from Wilson Research Group. There is much less coverage and analysis of the EDA world available today than there used to be, so we all applaud Mentor’s willingness to fund this survey and share the results.
Hemendra’s focus is on the well-known phenomenon of verification consuming more and more of a chip project’s resources. It is not uncommon to find that SoC projects have two or three verification engineers for every design engineer. So what do these verification engineers do with all their time and resources? The interesting result from the Mentor survey is that verification engineers spend 36% of their time on debug. At Breker, we’ve given a lot of thought about how to reduce debug time and effort, so we’d like to share some thoughts.
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Tags: assertions, Breker, constrained-random, constraints, EDA, functional verification, graph, scenario model, simulation, SoC verification, system coverage, test generation, TrekSoC, TrekSoC-Si
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Tuesday, February 4th, 2014
Our last post on the relationship between the Universal Verification Methodology (UVM) and Breker’s technology was very popular. In only a week, it has become the fifth-most-read post in the nine-month history of The Breker Trekker blog. Clearly people are interested in the UVM and what strengths and weaknesses it brings to the ever more complex world of SoC verification.
This week we’d like to continue the discussion with a topic that we did not address last week: how the UVM offers an alternative to running embedded code by replacing one or more of the processors in the SoC with a verification component (VC). Our CEO, Adnan Hamid, addressed this topic in an Electronic Design article last November. We’d like to revisit some of the key points of that article in the context of last week’s UVM discussion
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Tags: Breker, EDA, emulation, functional verification, reuse, scenario model, simulation, SoC verification, system coverage, test generation, TrekSoC, TrekSoC-Si, UVC, uvm, verification component, verification IP, VIP
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Tuesday, January 28th, 2014
When people first start reading about Breker and what we do, we make the point that transactional simulation testbenches are breaking down at the full-SoC level. Usually, we specifically mention the Universal Verification Methodology (UVM) standard from Accellera as not being up to the challenge of full-chip verification for SoC designs. We sometimes worry that someone will read into this that we don’t like the UVM, or Accellera, or even standards in general. Nothing could be further from the truth!
We have great respect for the UVM and other EDA-related standards developed by Accellera, IEEE, and other organizations. In this post, we’d like to discuss specifically what we see as the strengths and weaknesses of the UVM and explain how Breker’s technology complements rather than replaces this methodology. Yes, the UVM has limitations, and we address those with our tools and technologies. But the UVM forms a stable and standard base on which nearly all of our customers build their simulation-based verification environments.
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Tags: Breker, constrained-random, EDA, emulation, functional verification, graph, reuse, scenario model, sequencer, simulation, SoC verification, system coverage, test generation, TrekSoC, TrekSoC-Si, Universal Verification Methodology, uvm, VIP, virtual sequencer
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Tuesday, January 21st, 2014
Recently on this blog, a series of related posts from Breker, Jasper, and OneSpin discussed formal analysis and its potential for playing a greater role in the verification process. We think that it’s important for The Breker Trekker to address topics in verification beyond our own technology and to provide occasional commentary on technology and the world of EDA in general. However, this recent focus on formal has caused some readers to wonder whether we consider ourselves to be in the formal market.
The short answer is “no” but there is some overlap in the technologies that we use and the techniques employed for formal analysis. Regular readers know that the foundation for our products is a graph-based scenario model that captures both the intended behavior of your SoC design and your system-level test plan. We can automatically extract system coverage from this model, with the model and coverage interacting in interesting ways. Let’s consider to what extent this is formal technology.
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Tags: Breker, EDA, emulation, formal analysis, functional verification, graph, jasper, OneSpin, scenario model, simulation, system coverage, test generation, TrekSoC, TrekSoC-Si, use cases
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Tuesday, January 14th, 2014
Both our original post challenging Jasper Design Automation’s statement that “formal will dominate verification” and Jasper’s response have generated excellent readership. Another major player in the formal world, OneSpin Solutions, also has some strong opinions to share. Please join us in welcoming OneSpin’s Director of Marketing Dave Kelf with his guest post:
I would like to thank Breker for driving this debate on the future importance of formal verification. In my opinion, not only will formal dominate verification, but my belief is that the effect of this technology will be as transformational as the advent of logic synthesis.
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Tags: Breker, EDA, formal analysis, functional verification, graph, jasper, OneSpin, scenario model, simulation, SoC verification
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Tuesday, January 7th, 2014
This week’s blog post is inspired by Brian Bailey’s recent article “Making Modeling Less Unpleasant.” I noted with amusement that the link to his article ends with “making-modeling-pleasant” which I suspect was automatically generated from an early draft. So perhaps Brian started with the idea that modeling could be pleasant, but concluded that “less unpleasant” is as good as it can get? Is he too pessimistic? Can modeling actually be pleasant?
It depends in part on what aspect of design or verification modeling we consider. Brian’s primary focus is on system-level models of the design, also called electronic system-level (ESL) models, architectural models, or virtual prototypes. The appeal of a simulatable SoC model fast enough to run compiled code, capable of both functional and performance verification, is easy to understand. There have been many attempts to establish standard approaches, such as transaction-level modeling (TLM), and languages, such as SystemC.
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Tags: Breker, EDA, formal analysis, functional verification, graph, SoC verification, system coverage, test generation, use cases, uvm
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Monday, December 30th, 2013
Please allow me to start this post with a sincere wish for all of our readers to have a happy and healthy holiday season. There are many enjoyable activities both sacred and secular this time of year, something for everyone whatever your personal beliefs. I hope that you all have the chance to relax a bit and share some delicious food with family and friends.
I thought about writing a column on the top 5 holiday wishes for verification engineers, but I felt that it would be a bit presumptuous to speak for you. We do work very hard to understand what you need in order to tailor our products to gaps in your verification process and speed up your project. Therefore, I’m going to offer 5 gifts for you, the verification engineer, that are available with Breker’s products. I hope that you like them!
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Tags: applications, Breker, EDA, emulation, functional verification, graph, production software, reuse, scenario model, simulation, SoC verification, system coverage, test generation, TrekSoC, TrekSoC-Si, use cases, uvm, verification IP, VIP
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Tuesday, December 17th, 2013
With due apologies to Barbra Streisand, the topic of today’s blog post is the verification of SoC memories and memory subsystems. Once upon a time, memories were considered just about the easiest design structure to verify. A simple automated test doing “walking 1s” and “walking 0s” supplemented by some random reads and write to random addresses with random data seemed to be good enough.
“Can it be that it was all so simple then? Or has time re-written every line?” Actually, it really was that simple back then. But a lot of changes in memory subsystems have come along to complicate matters: memory regions, caches, multi-processor designs, shared memory, complex memory maps, etc. Verification of memories today is much more challenging, with many corner cases to be exercised, but it’s an essential part of the overall SoC verification effort.
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Tags: Breker, buffer, cache, coherency, constrained-random, emulation, functional verification, graph, memories, memory map, scenario model, streisand, system coverage, TrekSoC, TrekSoC-Si
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Tuesday, December 10th, 2013
As you likely know by now, Breker’s primary focus is on verifying SoCs with one or more embedded processors. Sometimes these processors are homogenous, most commonly either the Intel/AMD x86 or ARM architecture. Other SoCs have multiple heterogeneous processors, possibly a diverse mix of cores from x86, ARM, MIPS, ARC, Tensilica, etc.
The trade press devotes a lot of virtual ink to covering the “war” for embedded processor dominance. An article last week made the case for ARM winning. A recent white paper discussed “heterogeneous multi-processing” using ARM’s “big.LITTLE” approach of multiple cores with the same architecture but different performance characteristics. Another article reminded us not to forget about DSPs in the heterogeneous mix. The same could be written about GPUs. So what is Breker’s take on all this?
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Tags: AMD, ARC, ARM, Breker, DSP, EDA, functional verification, GPUs, Intel, IP, Synopsys, Tensilica, verification IP, x86
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Wednesday, December 4th, 2013
As I hoped, my recent post challenging Jasper Design Automation’s statement that “formal will dominate verification” has drawn very good readership and generated some stimulating industry discussions. Today, Joe Hupcey III from Jasper responds and offers more ammunition for their claims of dramatic recent advances in the power and usability of formal technology:
Thanks to the folks at Breker for the comments and analysis in your post asking “Will Formal Really Dominate Verification?” in reference to Jasper’s recent assertion of formal’s ascendancy. As your thoughtful post acknowledges, verifiers are seeing formal starting to take over block and unit level verification, as well as select system-level applications. Indeed, the industry has seen this movie twice before – specifically, the growth of emulation into the mainstream and again with constrained-random simulation.
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Tags: Breker, constrained-random, EDA, formal analysis, formal apps, jasper, Moore's Law, simulation, SoC verification, uvm
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