UVM is Dead! Long live UVM+PS!

When the forebears of SystemVerilog and UVM were being created, the world was a different place. Verification was primarily directed testing and code coverage was good enough to signal completion. Development of directed tests was getting to be slow, cumbersome and difficult to maintain. Languages and tools were created that added the ability to randomize stimulus but that created two problems. First, you had no idea what a test had accomplished and second, you had no idea that the design had actually reacted in the right manner. Thus, two additional models became necessary: a combination of checkers and scoreboard and the coverage model. The big problem was, and remains, that the three models are independent models only unified by a thin layer of syntax.

A lot has changed in that time. A block today is larger and more complex than complete designs back then. Functional coverage was hailed as being a big advance. Coverage was no longer determined by what the design contained and became a notion of what the design should do. Code coverage was seen as being devoid of the notion of system context, a complaint that is now being hurled at functional coverage as well. Users feel it is becoming increasingly difficult and time consuming to capture effective coverage models.

It’s time for a do-over! System-level verification is primarily performed using directed testing today and needs to evolve. At the same time, a lot of block-level verification is beginning to take on characteristics of system-level verification, including multiple embedded processors, and there is a need to extend the reach of verification into the spaces of power, performance, safety and security. System-level verification needs a new way to describe coverage, new ways to add randomization and new ways to confirm the desired functionality exists in the design. It is this problem that brought about the development of graph-based verification methodologies and the development of the Portable Stimulus Standard.

Is this the end of the line for UVM? Aspects of UVM  are worth keeping and a huge library of transactor models exists within the industry. Those have to be preserved. We do not need to preserve UVM’s archaic notions of sequences, scoreboards and coverage and, thankfully, there is a much better way to accomplish those. And better still, it can be done in one unified model! As an added benefit, that model can reach into the whole design and verification flow from conception through to silicon.

Curiously, you don’t hear much about parts of this from the large EDA companies. They only talk about Portable Stimulus as a better way to provide stimulus into UVM models or to drive emulation. Portable Stimulus is a complete model of verification intent that can and should replace the way that stimulus is generated. It should replace existing scoreboards and should be the basis for a new coverage model. When unified in this manner, it starts to look like a true act of verification because that one model of verification intent spans all of the functions necessary.

The large EDA vendors published articles and whitepaper showing how stimulus can be generated from Portable Stimulus and how it can drive UVM transactors. They offer scant information about how result checking is done within Portable Stimulus or how system-level coverage is defined by the graph. Perhaps this is because they want to prolong the life of their existing UVM-based tools as long as possible. Tools such as those are based on functional coverage or used for verification planning based on random stimulus.

Or, they have much deeper reasons why they may intend to keep the existing methodology in place for as long as possible. SystemVerilog-based verification solutions need a constraint solver to run along with the simulator. They generate the next piece of stimulus at each step of the simulation. Many figures show that as much time is spent in the testbench as it is in the simulator making your simulation seats only half as effective. And this happens every time you rerun the same test as part of your regression suite.

Did you know that Portable Stimulus can generate the entire system-level test upfront? Once! That means your simulator becomes almost twice as effective and you only need to renew the license on half of them. Or, you suddenly have the ability to run twice as many simulations on the existing licenses. Did you know that Portable Stimulus can tell you the coverage a test will generate before it runs? That means you can select only the most important tests before you even run the simulation. Did you know that Portable Stimulus can start generating tests before the testbench is complete? You can start the verification process a lot earlier.

Each of these changes reduces the value of their existing tools, so it should come as no surprise that they don’t want to talk about these aspects much.

Perhaps you should ask your vendor which aspects of Portable Stimulus they intend to support. Supporting the language is only half of the issue. Ask them about the business model that goes along with the adoption of graph-based verification flows. Ask them if they can pre-generate complete tests ahead of time so they don’t slow down your simulations. Ask them if they support unified coverage on the graph – which also enables much better integration with formal verification. Ask them how they are going to deliver the full value of a UVM+PS flow.

Breker has none of these conflicts and will deliver the best total value in a solution. Together we can do this.

For more on Portable Stimulus and System-level Coverage, please join us at DVCon US at the DoubleTree Hotel in San Jose, February 26^th – Mar 1.  I will be presenting during an Accellera-sponsored tutorial titled, “Portable Test and Stimulus: The Next Level of Verification Productivity is Here,” Monday from 9 a.m. until noon.  Breker has also organized a panel on “Help! System Coverage is a Big Data Problem!,” Wednesday at 8:30 a.m. to 9:30 a.m., to be moderated by Brian Bailey, technology editor at Semiconductor Engineering.  Visit the Breker booth #304 during the exhibit hours: Monday 5:00 – 7:00 pm, Tuesday 2:30 – 6:00 pm, Wednesday 2:30 – 6:00 pm

Tags: portable stimulus, SystemVerilog, uvm, UVM+PS

Category: Knowledge Depot

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