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Archive for July 15th, 2010

Japan & SystemC

Thursday, July 15th, 2010

With all of the excitement in the “front end” of the SOC design/verification/modeling community about Accellera’s UVM, it is easy to loose track of work being done around another significant front end language—SystemC.  For those not aware, there is an IEEE group (P1666-2011) that is working diligently on updating the very popular 1666-2005 release of SystemC that was originally developed by OSCI.  The charter of the current IEEE SystemC group is to add clarifications and fix errata in the 2005 standard, add  TLM 2.0 and formalize the description of the TLM 1.0 message passing facility.  There will likely also be several new features added that do not already exist in the OSCI version of SystemC, including process control extensions.  Work is expected to wrap on this new version of IEEE SystemC in late 2010, with final approval in the first half of 2011.

The “entities” that belong to this IEEE SystemC P1666 committee are Accellera, Cadence, Freescale, Intel, JEITA, Mentor, NXP, OSCI, ST Micro, STARC, Synopsys and Texas Instruments.  Note that this is a very geographically diverse group, with representation from the US, Europe and Japan.  Indeed, when I (as chair of the group) hold a P1666 teleconference, I typically find in the conference call summary report more than 10 different country codes for the phone numbers of the attendees (including non-member observers).


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