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Archive for May, 2010

Karen Bartleson’s Book & The Nature of Standards Groups

Friday, May 28th, 2010

Karen Bartleson’s book on Standards, for which I was pleased to write a blurb for its front pages, is now out:  As I indicate in my blurb, Karen’s book does a very good job of illuminating the sometimes murky world of Standards, EDA and otherwise.

It may seem odd that I would highlight and praise a book written by an employee of a major rival.  In fact, for those whose views of Standards are centered around the so-called “Standards Wars”, this may appear really odd.  Indeed, in the heyday of EDA journalism, periodically such “wars” played out on the front pages of various “newspapers”.  Because of this, there are many who still view EDA Standards groups as places where the basic tenor is one of conflict between the participants.

There is some reason behind this perception.  To paraphrase Karen 5th commandment: “Realize there is no neutral party”.  A company like Cadence, for which I work, or Synopsys, for which Karen works, spends enough (between dues and cost of participating employees) on EDA Standards to fund a nice-sized engineering group(s).  They (and multiple other companies, including companies that use EDA standards) spend large sums in this area precisely because EDA Standards are critical to their business interests.  Hence, they are not neutral to the results that come out of the Standards groups, and no one ought to be surprised when conflicts of interest occasionally erupt into a “war”.

But this is only a small part of the picture, and ignores the overarching cooperative nature of Standards activities.  Indeed, in what other forum can one find representatives from Cadence, Synopsys, Mentor and other EDA companies working in a (for the most part) cooperative manner?  Moreover, it is not only EDA companies that sit with their competitors at these meetings: it surprises no one to find companies like Intel, AMD and ARM sitting side by side in a Standards meeting.  At the end, the fact that competitors are willing to sit down with each other, and are often willing to extend non-discriminatory licenses on reasonable (often no cost) terms to what was previously proprietary technology, reveals the essential nature of a standards meeting—it is a tension-filled peace conference, not the battlefield itself.

Welcome to UVM 1.0 EA and to

Monday, May 24th, 2010

This is the first of an ongoing series of posts related to EDA Standards activities.  In some cases I’ll be highlighting “standards happenings”, while in other posts I’ll speak out about various developments in the EDA Standards world.  I expect to use my 25+ years in Standards activities to help shed light on an area that is often murky to the uninitiated.

This initial post comes at an excellent time for the EDA Standards world, because it coincides with the release of the Accellera Universal Verification Methodology 1.0 Early Adopter (“UVM 1.0 EA” to those in the know).  The UVM, for those who are not aware, is designed to enable the development of interoperable Verification IP (VIP) in SystemVerilog.  Currently there are two dominant “Verification Methodologies”, the OVM and the VMM.  While the Accellera VIP Technical Subcommittee (TSC) created a “best practice” in 2009 for allowing VMM VIP to operate in an OVM environment (and vice versa), it was felt that an industry standard Verification Methodology was required.  Thus was born the UVM, developed using OVM 2.1.1 as a base with additional functionality taken from the VMM.  The expectation is that as time progresses, the interoperability of VIP will become increasingly less of an issue, because more inter and intra-company project teams will be using the same Universal Verification Methodology.


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