Fig. 1. Process and device simulation of a SiC power trench MOSFET.

A quick search of the IEEE Xplore online library gives  a list of more than 230 published technical articles on Power Device Simulation using Silvaco TCAD. Here are some recent papers with the authors' abstracts that cover silicon-carbide (SiC) and Junction-Less Double Gate MOSFET devices. Any mention of 'we' or 'our' refers to the paper's authors:

Study of oxide trapping in SiC MOSFETs by means of TCAD simulations, Materials Science in Semiconductor Processing, Volume 97, July 2019, Pages 40-43

“SILICON CARBIDE (SiC) material has attracted substantial attention during the last few years as a promising candidate for making power devices for high-temperature operation and under harsh environments. In spite of the considerable progress in device performance, reliability may be a limiting factor for the introduction of SiC MOSFETs in commercial power devices. One of the major reliability concerns is the instability of the threshold voltage in MOSFETs and, similarly, of the flat-band voltage in capacitors under normal operation conditions. This instability is attributed to trapping of channel electrons in interface and bulk oxide traps.

“The main goal of this work is to investigate how the trapped charges at SiO2/SiC interface influence the C/V curve. In particular, by means of 2-D numerical simulations (SILVACO tools), we could isolate the two different contributions from p-type and n-type doped regions of our MOSFET and we considered both donor and acceptor traps contributions. Then, we compared the simulation results with experimental C/V curves. A good agreement between TCAD simulations and experimental measurements was obtained. So, device simulations can provide a better understanding of such defects at SiO2/SiC interface and we give an insight into the influence of traps, produced during device processing or caused by radiation environment, on the output characteristics of the device.”

Read the rest of 230 Papers on Power Device Simulations using Silvaco TCAD

When we think of research and development in the Microelectronics industry, we typically think of East Asia, the United States and Europe.  However there is a long time conference held in South America called “Chip in [location].”

The “Chip in” is a series of events that started in 2000 with the “Chip in the Jungle”, in the state of Amazon, Brazil. It is the largest conference in Microelectronics in South America, annually held in Brazil. The conference goal is to bring together managers, leading researchers from academia and industry, and students to present and discuss relevant issues related do the major Microelectronics research and development areas.

This years event takes place in São Paulo, SP, Brazil, August 26 to 30, 2019.   Sampa is a nickname for São Paulo, so this year's conference is called “Chip in Sampa.”  The conference consists of three symposiums, a workshop and student forum.  They are listed here

• 34th SBMicro – Symposium on Microelectronics Technology and Devices
• 32nd SBCCI – Symposium on Circuits and Systems Design
• 9th WCAS – Workshop on Circuits and Systems
• 4th INSCIT – Symposium on Instrumentation Systems, Circuits and Transducers
• 19th SFORUM – Undergraduate-Student Forum

One of the invited talks for the Symposium on Circuits and Systems Design is by Bernardo Culau, Director of Characterization, Silvaco, Brazil  and takes place on Friday, Aug. 30.

His talk will be on the topic: On-Chip Variation and the Sign-off Timing Flow: An Industry Perspective Read the rest of On-Chip Variation and the Sign-off Timing Flow at “Chip in Sampa”, Aug. 26-30

The Stellar GUI-based field solver tool for parasitic extraction is now integrated into Hipex, Silvaco’s full chip extraction tool. In Hipex, users have a choice of which RC extraction field solver mode to use including Stellar. The Expert editor GUI has been extended to provide technology setup for the Stellar mode of Hipex. Stellar can handle very large layouts with a smaller memory footprint and reduced runtime with acceptable accuracy in comparison to the Clever reference field solver. Clever employs an ultra-accurate adaptive meshing field solver, and can be used as an accuracy check when Stellar or rule-based parasitic extraction is performed in Hipex.

The Stellar GUI-based field solver tool for parasitic extraction is now integrated into Hipex, Silvaco’s full chip extraction tool. In Hipex, users have a choice of which RC extraction field solver mode to use including Stellar. The Expert editor GUI has been extended to provide technology setup for the Stellar mode of Hipex. Stellar can handle very large layouts with a smaller memory footprint and reduced runtime with acceptable accuracy in comparison to the Clever reference field solver. Clever employs an ultra-accurate adaptive meshing field solver, and can be used as an accuracy check when Stellar or rule-based parasitic extraction is performed in Hipex.

On August 15, 2019, 10:00am to 11:00am (PDT) Silvaco will have a webinar titled: “Fast Capacitance Extraction Within the Expert Layout Editor Using Hipex and the Stellar Solver for a Touch Panel Application.” It will review the basic interface of Hipex in the Expert editor GUI using Stellar as a field solver to extract capacitance for a touch panel application example. Read the rest of Webinar: Fast Capacitance Extraction for a Touch Panel Application, Aug. 15

Fig. 1. DNA Analysis of IP Fingerprints

In the world of SoC development, an IP management system is software for the licensing, distribution and compliance administration of design IP for both vendors and consumers of IP.

In May 2019, Silvaco was awarded a patent for System and Method for IP fingerprinting and IP DNA analysis. This patent reflects a little of the unique technology in the Xena® IP Management System from Silvaco.

What is IP fingerprinting? An IP fingerprint is a unique signature for an individual IP that allows for the detection of that individual IP in an SoC . What's interesting about this is, unlike other methods like tagging, there's no modification of the IP, and there's no modification of the design flow.

Read the rest of System and Method for IP Fingerprinting and IP DNA Analysis

The Silvaco SURGE 2019 Global User Conference was successfully held on July 19, 2019 at the Kerry Hotel in Pudong, Shanghai! More than 200 guests from panel display, semiconductor product design and manufacturing, semiconductor industry associations, universities and research institutes attended the conference. The guests actively shared industry trends and conducted face-to-face technical exchanges with technical experts from Silvaco's US headquarters, Japan, Korea, Taiwan and Shanghai to discuss innovative applications of semiconductor technology from Atoms to Systems. Silvaco Interim CEO Babak Taheri said: “These events open up important conversations with industry leaders and peers, highlight smart solutions to real-world challenges, and provide insight into current and future trends.”
SURGE China 2019 had 21 topic presentations in three session covering the topics of Display, IC / IP, and Foundry, and two keynote talks.

Read the rest of Great Success for China Silvaco UseRs Global Event (SURGE) in Shanghai

In the following video, Dr. Firas Mohamed, VP & GM, Machine Learning & Flow Optimization Division and GM, Silvaco France talks with Graham Bell about Machine Learning technologies deployed in Silvaco EDA tools at the SEMICON West 2019, July 9 – 11 at Moscone Center in San Francisco. A transcript of the video is also below.

Read the rest of Machine Learning in Silvaco EDA Software

In the following video, Wally Rhines, CEO Emeritus, Mentor Graphics speaks with Graham Bell about the worlds of Design and Manufacturing meeting at SEMICON West and ES DEsign West, a co-located event, July 9 – 11 at Moscone Center in San Francisco.  Wally also brings the audience up to date on how Mentor is doing after the acquisition by Siemens. A transcript of the conversation is below.

Read the rest of Wally Rhines on the Convergence of Design and Mfg., and Mentor Graphics Update

Silvaco Inc. is pleased to announce the SURGE (Silvaco UserRs Global Event) Shanghai schedule.

SURGE brings together users, developers, and industry experts of the EDA, IP and TCAD communities to discuss new semiconductor technologies, smart integration for innovative applications and new techniques for realizing advanced designs. According to CTO Babak Taheri, “These events open up important conversations with industry leaders and peers, highlight smart solutions to real-world challenges, and provide insight into current and future trends.”

Presentations

A variety of presentations will cover IP deployment, semiconductor simulation, and design verification. Roadmaps and exciting technology updates will also be included. Discover how Silvaco solutions are used to realize silicon success in Consumer, Datacenter, Automotive, and IoT markets.

Keynote Speakers and Panelists

Hear from industry leaders and visionaries who influence the global electronics marketplace. They will discuss trends in systems, silicon, and applications and share their thoughts on the nanometer challenges and opportunities that face us today.

Live Demonstrations

Get a more in-depth look at specific Silvaco products, new solutions, and feature enhancements to enable semiconductor innovation and deliver products faster and smarter.

Networking Opportunities

Engage in stimulating technology discussions with peers and industry experts at SURGE and stay connected after the event.

Location
Kerry Hotel, Pudong, Shanghai
Shanghai Ballroom #2
1388#, HuaMu Road,
Pudong New area,
Shanghai China

Read the rest of 23 Presentations and More at Silvaco UseRs Global Event (SURGE) in Shanghai, July 19

“It's been amazing how fast we've been able to turn out new libraries, new spins, new corner models with your tools.”

I interviewed Silvaco partner Stephen Fairbanks, CTO of Certus Semiconductor from the show floor at DAC 2019, in Las Vegas, about I/O Design and Characterization.  He talks about using the Viola characterization tool from Silvaco for a complex part while under time pressure to produce an accurate model. A full transcript of the conversation is below.

Graham Bell: We're at DAC in Las Vegas. It's warm outside, but we're inside here talking about I/O and how I/O is involved with different aspects of chip design. Certus Semiconductor provides I/O services and I/O products for IC designers. Now, you mentioned off camera that I/Os are free from the IC Foundries, so how can you make a business when somebody else is offering free?

Stephen Fairbanks: That's an excellent question. We've been doing this for 12 years now. And yes we do, we compete with free, because you can get I/Os and you can get ESD libraries from the Foundries for free, and even a lot of the IP core suppliers will offer I/Os as part of their packages. We have found a niche. Because what's happened as technologies progressed, the interfaces have become more complex. Companies need more features in a single product, they need more voltage domains, more power capabilities; they need power down modes, and they need I/Os to serve multi-role purposes, and we can help them do that. And another feature is area, especially in the realm of IoT and consumer electronics this is a big issue. We are always able to optimize our customers' packages, packaging, pad rings by tailoring the I/O to their particular cost and product needs. So in those areas, we can beat the foundries every time.

GB: That's great. Now we have a new verification solution called Viola 10X, and that's been used in at least one application I think that you're aware of. Can you share your experiences with our new Viola application? Read the rest of I/O Design and Characterization – How Can You Compete with Free?

New system-on-chip (SoC) devices are driving new memory architectures and photonic interfaces, while specialized new intellectual property (IP) requires analysis down to the nanometer and atomic levels because of single nanometer process nodes. According to Babak Taheri, CTO and EVP of products at Silvaco, a leading EDA Software, semiconductor IP company, a member of SEMI and the ESD Alliance, a SEMI Strategic Association Partner, design technology co-optimization and proven IP are required for this analysis.

Taheri recently discussed atoms to systems in next-generation SoC designs with Nanette Collins ahead of ES Design West, co-located with SEMICON West, July 9-11 at the Moscone Center in San Francisco.
Read the rest of Taking Atoms to Systems in Next-Generation SoC Designs