As technology advances and the complexity of circuit designs continues to grow, analog simulation can easily become the bottleneck for design verification. In order to cope with this increasing pressure on the simulator’s performance, SmartSpice provides a scalable simulation engine: HPP (High Performance Parallel).
In this webinar, we describe how SmartSpice HPP takes advantage of the modern multicore hardware platforms to speed up all internal aspects of transient simulations of analog circuits by adopting a partition-based simulation.
