Secure Autonomous Driving Webinar

Silvaco has an upcoming webinar IP Solutions for Secure Autonomous Driving on Dec. 3, 10am – 11am (PST) .

The webinar will present the risks and necessary countermeasures for securing cyber-physical vehicle systems. Manufacturers are pressured by customer demands and market competition to rapidly integrate the latest features into their vehicles, including Infotainment, 5G network connectivity, advanced driver assistance systems (ADAS), and autonomous driving. Increased vehicle-to-everything (V2X) connectivity exposes access to critical vehicle networks. ADAS and autonomous driving features yield physical control of a vehicle to software subsystems. These enhanced vehicles demand security hardening to guarantee the safety of pedestrians and motorists.
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Silvaco’s CEO Babak Taheri enjoys telling the chip design community to think in terms of atoms for their next design project. In fact, he is urging the entire semiconductor ecosystem to consider the atomic level when designing next-generation SoC devices. In his view, these SoCs are driving the need for new memory architectures and photonic interfaces. He uses new, specialized IP as another example because IP requires analysis down to the nanometer and atomic levels on account of single nanometer process nodes.

Babak takes his talk, “Next Generation SoC Design: From Atoms to Systems,” next week to SMART Design, the first system-centric series showcasing advances in electronic system design to be held at SEMICON Europa. SEMICON Europa will begin Tuesday, November 12, through Friday, November 15, at Messe München in Munich, Germany. SMART Design is scheduled for Thursday, November 14, from 14:30 until 17:30 in TechARENA 1, Hall B1.

According to Babak, common wisdom dictates that each new chip design is more complex than the last and none is more complex than those currently under development. These new SoC devices for mobile phones, automobiles, intelligent edge nodes, big-data compute and storage are using AI and ML technologies that drive new bandwidth limited compute, data flow, and memory architectures. Some require photonic interfaces.

One common denominator is the number of IP blocks. On the average, more than 85% of them are reused because it’s costly to make these chips again and again with new IP. Some estimates predict only 10% of IP used in an SoC design by 2025 will be new. Technologies that use and reuse design IP at the architectural level –– up to 90% –– include Flash memory, other advanced non-volatile memory technologies such as MRAM, RRAM and SoCs as well as NVIDIA’s Xavier and Apple’s A13. (more…)

The same day we hosted the Silvaco Users Group event (SURGE) in Silicon Valley on October 24, we also had an online webinar on artificial intelligence (AI) and machine learning (ML) SoCs from a memory and interconnect IP perspective. This webinar discussed the challenges of developing AI-based and ML-based SoCs and the novel architectures needed for AI and ML applications to meet efficiency requirements. These include specialized processing, high bandwidth and low-energy memory throughput, and reliable high-performance connectivity. The webinar also discussed the efficient customization of memory and interconnect IPs for successful development of AI and ML SoCs.

To register and view this pre-recorded event, go to the AI and Machine Learning SoCs – Memory and Interconnect IP Perspectives page.

Presenter

Ahmad S. Mazumder is the presenter for the webinar. He is a principal field application engineer in IP Engineering division of Silvaco. He is responsible for development and customer support in all analog and interface IPs. He is an industry veteran on the development of high-speed memory, interface IPs, and many types of analog IPs. He worked on cutting edge DDR, extreme high-speed SerDes, interfaces, ESD, and QoR for 24 years at various SoC companies (Intel, Broadcom, C-Cube Microsystems, etc). He recently joined Silvaco’s IP Engineering division.

Ahmad S. Mazumder holds a MS in VLSI Semiconductor Design from the City University of New York and BS in Electrical and Electronics Engineering from Bangladesh University of Engineering and Technology.