Everything You Want to Know about Silvaco Foundation IP

In the creation of an ASIC or SoC a wide variety of digital components are needed. Standard logic cells are used to implement the high-level description of the chip which is typically written in RTL.  A synthesis tool such as Design Compiler or RTL Compiler is used to generate a gate-level netlist built out of the standard logic cells from a cell library. Communication on and off of the chip, requires unique input/output cells or I/Os that can drive off-chip wiring and withstand electrostatic discharges in the range of thousands of volts.  The other main category is digital memories typically SRAMS that can take up a significant amount of area on the die for a chip.  These 3 categories of digital design IP are called Foundation IP.

Silvaco offers a complete portfolio of SIPware Foundation IP  for the creation of ASICs and SoCs for almost any process node.  For over 20 years, the Nangate team, now a part of Silvaco, have been providing Foundation IP to the design community. They pride themselves in offering the best-in-class components with a full set of services which is a one-stop shop for chip developers and foundries.

Standard Cell Library Foundation IP
Today’s foundries offer a wide variety of process nodes ranging in size from 250nm, and above, down to 7nm and below. Process nodes of 110nm, and above, are considered mature since they have been in the market for over 20 years.

The standard cell libraries that were developed earlier at that time do not include recent technology developments. Here is a list of how standard cells and process offerings have changed over this time:

• Tapless architecture
• Clock gating
• Vt variants.
• Power management kits (PMK) & multi-power islands
• Multi-bit FFs
• Fine grain sizing
• Complex function matching

This means that legacy libraries can be further improved for power footprint, performance and area.

With 700 – 1,200 standard cells and multi VTs  and track heights, the Silvaco standard library offers thousands of cell variants, enabling applications from ultra-low power to high-speed. Silvaco carefully sizes each cell family in the library, optimizing transistor sizes, P/N ratios and drive strength granularity for further power and performance gains. Silvaco’s EDA platform for Layout Optimization, Cello, enables a new level of optimization, with 35% area and 20% power reduction compared to off-the-shelf libraries from other vendors. Multi-bit and multi-height standard cells boost routing density even further by reducing pin count and packing more functionality inside standard cells. For instance the detailed review and exploration of 180nm design rules by Silvaco engineers resulted in the creation of a cell architecture that achieves a raw gate density of 162K gates per square millimeter.

The Silvaco library is extended with a Power Management Kit, taking power reduction to the next level with features such as multi-voltage design and power gating. Libraries are characterized for multiple PVT corners with extended voltage range and are compatible with multiple foundries.

I/O and ESD Protection Foundation IP

Silvaco has partnered with Certus Semiconductor for I/O and ESD cells and associated development services. Off-the-shelf I/Os from foundries or design IP provider provide basic performance without optimization for power, features or area. Modern interfaces are a complex mix of voltage domains, power modes, and must serve multiple purposes that challenge design teams. Certus provides optimization services for this complex mix of operating requirements, while keeping device area to a minimum. Certus optimizes the entire I/O system, including packaging, pad rings by tailoring the I/O, and ESD cells to cost and product needs. Multiple proven I/Os and ESD cells for various foundries are available off-the-shelf.

Our area of expertise includes the following:

• RF ESD:  Low capacitance RF ESD solutions, tailored to a customer’s specific design
• Wired High-Speed Interfaces (HDMI, LVDS, USB, TIA’s, XAUI, and 28Gb SERDES):  Extreme ESD robustness and unique needs, such as 5V tolerance, fail safe, EOS, and  low capacitance for optimal signal integrity
• Multi-Voltage Digital I/Os: GPIOs, fail safe GPIOs, and open-drain IOs (ODIO)
• Multi-Protocol I/Os:  Single IO designs that can comply with multiple electrical standards, reducing PAD cell counts, simplifying product variants, and helping customers target broader application spaces with single designs
• High Voltage Solutions: Unique techniques for 10V, 20V, and larger voltage structures on low voltage CMOS processes; optimize ESD in BCD processes
• Rad-Hard/High-Temp:  Certus has experience developing custom I/O’s with rigorous temperature and radiation tolerance requirements
• Custom IO: Optimized for power, area, modes, and features

On-chip Memory Foundation IP

Silvaco has partnered with Mobile Semiconductor for memory Foundation IP. We offer leading edge SRAM, ROM, and register file compilers optimized for applications requiring ultra-low power, low leakage, or ultra-high performance. Our low voltage SRAMs can operate at minimal voltages and have ultra-low power standby capabilities to extend effective battery life of end products.

Applications include:

• Internet of Things (IoT) consumer and commercial products
• Low power digital signal processing (DSP)
• Low power networking applications using standards such as Bluetooth Low Energy (BLE)

We have over fifty memory compilers targeting processes ranging from 90nm down to 12nm.  At the 28nm node, there are sixteen different compilers, many of which were sponsored by GlobalFoundries.  Their low power technologies include:

• Clock Gating: Reduces dynamic power of memory banks composed of multiple memories
• Dual Voltage: Level shift between periphery and array supplies supports low voltage digital logic to reduce dynamic power. Supplies fully isolated for power off
• Speed Grades: Select the optimum speed/leakage tradeoff enabling both high speed and low power retention mode
• Optional Power Switches: Provide maximum flexibility for power down modes with easy integration including output isolation
• Five possible power modes

Summary
This has been a quick tour of the available Foundation IP from Silvaco. Our standard cell libraries support multiple Foundries, multi-Vt, multi-bit FFs and come with come with standard and custom PVT corners. For each library, add-ons include Power management kits (PMKs) and ECO Kits with fixed pattern for FEOL layers. Through our platform Cello we offer library creation, migration and optimization services down to 7nm process nodes.  To find out more about our custom services or our ready-to-go Foundation IP:
º  6/7/9/10/12 track libraries for the 180/152nm, 130/110nm, 90/80nm, 65/55nm process nodes
º  7/8/9/10/12 track libraries for the 40nm and 28/22nm nodes

For more information on Silvaco standard cell library Foundation IP, or I/O, ESD protection, and Memory Foundation IP, contact Sales@silvaco.com.

Category: Silvaco

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