In the creation of an ASIC or SoC a wide variety of digital components are needed. Standard logic cells are used to implement the high-level description of the chip which is typically written in RTL.  A synthesis tool such as Design Compiler or RTL Compiler is used to generate a gate-level netlist built out of the standard logic cells from a cell library. Communication on and off of the chip, requires unique input/output cells or I/Os that can drive off-chip wiring and withstand electrostatic discharges in the range of thousands of volts.  The other main category is digital memories typically SRAMS that can take up a significant amount of area on the die for a chip.  These 3 categories of digital design IP are called Foundation IP.

Silvaco offers a complete portfolio of SIPware Foundation IP  for the creation of ASICs and SoCs for almost any process node.  For over 20 years, the Nangate team, now a part of Silvaco, have been providing Foundation IP to the design community. They pride themselves in offering the best-in-class components with a full set of services which is a one-stop shop for chip developers and foundries. (more…)