Fig. 1. Process and device simulation of a SiC power trench MOSFET.
A quick search of the IEEE Xplore online library gives a list of more than 230 published technical articles on Power Device Simulation using Silvaco TCAD. Here are some recent papers with the authors' abstracts that cover silicon-carbide (SiC) and Junction-Less Double Gate MOSFET devices. Any mention of 'we' or 'our' refers to the paper's authors:
“SILICON CARBIDE (SiC) material has attracted substantial attention during the last few years as a promising candidate for making power devices for high-temperature operation and under harsh environments. In spite of the considerable progress in device performance, reliability may be a limiting factor for the introduction of SiC MOSFETs in commercial power devices. One of the major reliability concerns is the instability of the threshold voltage in MOSFETs and, similarly, of the flat-band voltage in capacitors under normal operation conditions. This instability is attributed to trapping of channel electrons in interface and bulk oxide traps.
“The main goal of this work is to investigate how the trapped charges at SiO2/SiC interface influence the C/V curve. In particular, by means of 2-D numerical simulations (SILVACO tools), we could isolate the two different contributions from p-type and n-type doped regions of our MOSFET and we considered both donor and acceptor traps contributions. Then, we compared the simulation results with experimental C/V curves. A good agreement between TCAD simulations and experimental measurements was obtained. So, device simulations can provide a better understanding of such defects at SiO2/SiC interface and we give an insight into the influence of traps, produced during device processing or caused by radiation environment, on the output characteristics of the device.”
When we think of research and development in the Microelectronics industry, we typically think of East Asia, the United States and Europe. However there is a long time conference held in South America called “Chip in [location].”
The “Chip in” is a series of events that started in 2000 with the “Chip in the Jungle”, in the state of Amazon, Brazil. It is the largest conference in Microelectronics in South America, annually held in Brazil. The conference goal is to bring together managers, leading researchers from academia and industry, and students to present and discuss relevant issues related do the major Microelectronics research and development areas.
This years event takes place in São Paulo, SP, Brazil, August 26 to 30, 2019. Sampa is a nickname for São Paulo, so this year's conference is called “Chip in Sampa.” The conference consists of three symposiums, a workshop and student forum. They are listed here
One of the invited talks for the Symposium on Circuits and Systems Design is by Bernardo Culau, Director of Characterization, Silvaco, Brazil and takes place on Friday, Aug. 30.
His talk will be on the topic: On-Chip Variation and the Sign-off Timing Flow: An Industry Perspective(more…)
The Stellar GUI-based field solver tool for parasitic extraction is now integrated into Hipex, Silvaco’s full chip extraction tool. In Hipex, users have a choice of which RC extraction field solver mode to use including Stellar. The Expert editor GUI has been extended to provide technology setup for the Stellar mode of Hipex. Stellar can handle very large layouts with a smaller memory footprint and reduced runtime with acceptable accuracy in comparison to the Clever reference field solver. Clever employs an ultra-accurate adaptive meshing field solver, and can be used as an accuracy check when Stellar or rule-based parasitic extraction is performed in Hipex.
The Stellar GUI-based field solver tool for parasitic extraction is now integrated into Hipex, Silvaco’s full chip extraction tool. In Hipex, users have a choice of which RC extraction field solver mode to use including Stellar. The Expert editor GUI has been extended to provide technology setup for the Stellar mode of Hipex. Stellar can handle very large layouts with a smaller memory footprint and reduced runtime with acceptable accuracy in comparison to the Clever reference field solver. Clever employs an ultra-accurate adaptive meshing field solver, and can be used as an accuracy check when Stellar or rule-based parasitic extraction is performed in Hipex.
In the world of SoC development, an IP management system is software for the licensing, distribution and compliance administration of design IP for both vendors and consumers of IP.
What is IP fingerprinting? An IP fingerprint is a unique signature for an individual IP that allows for the detection of that individual IP in an SoC . What's interesting about this is, unlike other methods like tagging, there's no modification of the IP, and there's no modification of the design flow.
The Silvaco SURGE 2019 Global User Conference was successfully held on July 19, 2019 at the Kerry Hotel in Pudong, Shanghai! More than 200 guests from panel display, semiconductor product design and manufacturing, semiconductor industry associations, universities and research institutes attended the conference. The guests actively shared industry trends and conducted face-to-face technical exchanges with technical experts from Silvaco's US headquarters, Japan, Korea, Taiwan and Shanghai to discuss innovative applications of semiconductor technology from Atoms to Systems. Silvaco Interim CEO Babak Taheri said: “These events open up important conversations with industry leaders and peers, highlight smart solutions to real-world challenges, and provide insight into current and future trends.”
SURGE China 2019 had 21 topic presentations in three session covering the topics of Display, IC / IP, and Foundry, and two keynote talks.
In the following video, Dr. Firas Mohamed, VP & GM, Machine Learning & Flow Optimization Division and GM, Silvaco France talks with Graham Bell about Machine Learning technologies deployed in Silvaco EDA tools at the SEMICON West 2019, July 9 – 11 at Moscone Center in San Francisco. A transcript of the video is also below.
One of the invited talks for the Symposium on Circuits and Systems Design is by Bernardo Culau, Director of Characterization, Silvaco, Brazil and takes place on Friday, Aug. 30.
The Stellar GUI-based field solver tool for parasitic extraction is now integrated into Hipex, Silvaco’s full chip extraction tool. In Hipex, users have a choice of which RC extraction field solver mode to use including Stellar. The Expert editor GUI has been extended to provide technology setup for the Stellar mode of Hipex. Stellar can handle very large layouts with a smaller memory footprint and reduced runtime with acceptable accuracy in comparison to the Clever reference field solver. Clever employs an ultra-accurate adaptive meshing field solver, and can be used as an accuracy check when Stellar or rule-based parasitic extraction is performed in Hipex.
