In the following video, Wally Rhines, CEO Emeritus, Mentor Graphics speaks with Graham Bell about the worlds of Design and Manufacturing meeting at SEMICON West and ES DEsign West, a co-located event, July 9 – 11 at Moscone Center in San Francisco.  Wally also brings the audience up to date on how Mentor is doing after the acquisition by Siemens. A transcript of the conversation is below.

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Silvaco Inc. is pleased to announce the SURGE (Silvaco UserRs Global Event) Shanghai schedule.

SURGE brings together users, developers, and industry experts of the EDA, IP and TCAD communities to discuss new semiconductor technologies, smart integration for innovative applications and new techniques for realizing advanced designs. According to CTO Babak Taheri, “These events open up important conversations with industry leaders and peers, highlight smart solutions to real-world challenges, and provide insight into current and future trends.”

Presentations

A variety of presentations will cover IP deployment, semiconductor simulation, and design verification. Roadmaps and exciting technology updates will also be included. Discover how Silvaco solutions are used to realize silicon success in Consumer, Datacenter, Automotive, and IoT markets.

Keynote Speakers and Panelists

Hear from industry leaders and visionaries who influence the global electronics marketplace. They will discuss trends in systems, silicon, and applications and share their thoughts on the nanometer challenges and opportunities that face us today.

Live Demonstrations

Get a more in-depth look at specific Silvaco products, new solutions, and feature enhancements to enable semiconductor innovation and deliver products faster and smarter.

Networking Opportunities

Engage in stimulating technology discussions with peers and industry experts at SURGE and stay connected after the event.

Location
Kerry Hotel, Pudong, Shanghai
Shanghai Ballroom #2
1388#, HuaMu Road,
Pudong New area,
Shanghai China

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“It's been amazing how fast we've been able to turn out new libraries, new spins, new corner models with your tools.”

I interviewed Silvaco partner Stephen Fairbanks, CTO of Certus Semiconductor from the show floor at DAC 2019, in Las Vegas, about I/O Design and Characterization.  He talks about using the Viola characterization tool from Silvaco for a complex part while under time pressure to produce an accurate model. A full transcript of the conversation is below.

Graham Bell: We're at DAC in Las Vegas. It's warm outside, but we're inside here talking about I/O and how I/O is involved with different aspects of chip design. Certus Semiconductor provides I/O services and I/O products for IC designers. Now, you mentioned off camera that I/Os are free from the IC Foundries, so how can you make a business when somebody else is offering free?

Stephen Fairbanks: That's an excellent question. We've been doing this for 12 years now. And yes we do, we compete with free, because you can get I/Os and you can get ESD libraries from the Foundries for free, and even a lot of the IP core suppliers will offer I/Os as part of their packages. We have found a niche. Because what's happened as technologies progressed, the interfaces have become more complex. Companies need more features in a single product, they need more voltage domains, more power capabilities; they need power down modes, and they need I/Os to serve multi-role purposes, and we can help them do that. And another feature is area, especially in the realm of IoT and consumer electronics this is a big issue. We are always able to optimize our customers' packages, packaging, pad rings by tailoring the I/O to their particular cost and product needs. So in those areas, we can beat the foundries every time.

GB: That's great. Now we have a new verification solution called Viola 10X, and that's been used in at least one application I think that you're aware of. Can you share your experiences with our new Viola application? (more…)

New system-on-chip (SoC) devices are driving new memory architectures and photonic interfaces, while specialized new intellectual property (IP) requires analysis down to the nanometer and atomic levels because of single nanometer process nodes. According to Babak Taheri, CTO and EVP of products at Silvaco, a leading EDA Software, semiconductor IP company, a member of SEMI and the ESD Alliance, a SEMI Strategic Association Partner, design technology co-optimization and proven IP are required for this analysis.

Taheri recently discussed atoms to systems in next-generation SoC designs with Nanette Collins ahead of ES Design West, co-located with SEMICON West, July 9-11 at the Moscone Center in San Francisco.
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“We've been working with Silvaco since we started the company 13 years ago. They've been a big part of our success. As of today, we're still using their Expert tool for the layout editor. All of our designs are done in Expert all the way down to 5 nanometer.”

– Randy Caplan, CEO, Silicon Creations

In the following video, I interview Silvaco customer Randy Caplan of Silicon Creations from the show floor at DAC 2019, in Las Vegas, about the latest trends and challenges for nanometer IC design success.  He talks about using a suite of Silvaco design tools down to the latest 5 nm silicon process nodes. A full ranscript of the conversation is below, as well.

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