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 Silvaco Nanometer Newsbyte

Archive for May, 2019

Display Week 2019: Featured Executive Video Interviews

Tuesday, May 28th, 2019

Silvaco did Executive Video Interviews at our booth in the middle of the show floor at Display Week 2019 in San Jose. We interviewed industry experts on what they expected for the Display industry in 2019 and what technical challenges that needed to be met. The interviews are displayed below. One video interview really stood out for me. Eddy Hsu, Director, Display Systems at Lumiode related how they were creating the future use Silvaco TCAD tools and had brought Lumiode to where it is today. It is the first one in the list.

Visit Silvaco's YouTube channel to see our collection of more than 70 different videos.

Eddy Hsu, Director of Display Systems at Lumiode

Eddy Hsu, Director of Display Systems at Lumiode

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Samsung Foundry and Silvaco Begin Partnership to Launch Samsung Foundry Semiconductor IP

Friday, May 17th, 2019

On Monday, May 13, Silvaco announced that the semiconductor design IP of Samsung Foundry is now marketed, licensed and supported through Silvaco. The addition of Samsung production-proven design IP complements Silvaco’s existing SIPware IP products and solutions—embedded processors, wired interfaces, bus fabrics, peripheral controllers, cores for automotive, consumer and IoT/sensor applications. The initial offering of hard design IP is for the 14nm process node and is expected to extend to advanced technology nodes at 11nm, 10nm and 8nm, as well as mature planar technologies such as 28nm.

Jaehong Park, executive vice president of Design Platform Development Team at Samsung Electronics said this about their design IP: “After identifying the requirements for different consumer, mobile, and HPC applications, we have compiled a full suite of design IPs which include wired and high-speed interfaces, analog and mixed-signal blocks and advanced security hard/soft cores. In partnership with Silvaco, we are bringing our proven IP to SoC engineers world-wide.”

Babak Taheri, CTO and EVP of Products at Silvaco talked about the importance of Samsung IP business: “Silvaco has an established track record, with multiple Tier 1 IP semiconductor companies, to unlock their assets and deliver their captive IP to the market. Silvaco has taken the next step and became a trusted partner of Samsung Foundry. With the launch of their IP we can now offer it to SoC design teams across the world.   Design IP is the fastest growing part of Silvaco’s business, and we expect accelerated growth with our Samsung Foundry partnership. I look forward to extending our collaboration with this premier foundry for current and future technology nodes.”

The Samsung Foundry hard and soft design IP will be offered by Silvaco starting in June 2019. If you would like to know more, go to our web-page Samsung Foundry IP. (more…)

SPICE Model Generation by Machine Learning

Tuesday, May 7th, 2019

It was 1988 when I got into SPICE (Simulation Program with Integrated Circuit Emphasis) while I was characterizing a 1.5 μm Standard cell library developed by students at my Alma-Mata Furtwangen University in Germany. My professor Dr. Nielinger was not only my advisor he also wrote the first SPICE bible in German language. At that time SPICE simulation was already established as the “golden” Simulator for circuit design for over a decade – and remains so to this day.

Of course, SPICE simulators went through several evolutions to adapt to the requirements of the most advanced technologies nodes, and SPICE models have been extended to be able to accurately reflect real silicon behavior; however, it seems that we are now at the point where it takes just too long to extend the models or come up with a complete new model for a specific material.

While over the first three decades only about half a dozen materials where used to manufacture semiconductors, ASM a leading semiconductor equipment manufacturer predicts that by 2020 more than 40 different materials will be in high volume production for the most advanced FinFET nodes at 7 and 5 nm.

This figure shows a 3D representation of a 10nm FinFET transistor front-end-of-line (FEOL) and back end of line up to MET1 already requires 14 different materials. A similar number of materials are required for full back end of line (BEOL) description. (more…)




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