A shift-left strategy to tackle the complexities of power domain leakage in IC design

Author: Matthew Hogan

A shift-left strategy to tackle the complexities of power domain leakage in IC design

Managing leakage power is a critical challenge for IC designers, as it can profoundly impact a device’s power, performance, area (PPA) and overall reliability. Leakage can manifest in various ways, from analog gate leakage causing high current drain to digital gate leakage leading to power management and reliability issues. Even subtle circuit changes can introduce leakage problems that compromise the final product. Traditionally, designers have left verification of these leakage issues until later design stages, resulting in costly rework. However, a shift-left approach that integrates leakage and reliability analysis into the pre-layout phase can help identify and address potential problems early on. By leveraging advanced EDA tools that take a holistic view of the circuit, designers can get ahead of leakage challenges and ensure their ICs meet the highest standards of quality and reliability.

Complexities of power domain leakage

Integrating multiple circuit cores into a single chip exposes reliability risks that can be conventional checking methods might miss. Even after exhaustively simulating individual cores, designers must still consider the overall reliability when these cores are combined.

Leakage can manifest in various ways and pose significant challenges. Analog gate leakage can result in high current drain due to improper states and unreliable outcomes. Digital gate leakage can cause power management and mismatch issues and low reliability due to floating inputs or under-driven states. Parasitic leakage pathways present an additional concern, potentially leading to long-term reliability risks, device degradation and poor power performance. Designers must verify leakage through parasitic body diodes and ensure proper biasing of PMOS and NMOS bulks.

Analog gate leakage

Eliminate high current drain by removing leakage from power supply to ground through MOSFET stacks, gate inputs floating and high impedance state. Low reliability is a result due to improper states and unreliable outcomes.

Digital gate leakage

Identify power management/mismatch issues, inputs under-driven (missing level-shifter) or floating in a high impedance state. These conditions lead to low reliability (improper states, unreliable outcomes) and high current drain.

Parasitic leakage

Identify long-term reliability risks, device degradation, short-term risks and poor power performance. Verify leakage through parasitic body diodes, bulks that are not biased high (PMOS) or low enough (NMOS).

Understanding these diverse leakage mechanisms and their impacts is crucial, as even minor circuit changes and have a profound impact on the overall quality and reliability of the final design.

IC design complexities that contribute to the risk of power domain leakage include:

• Power rails can be described as either internal (as a switched device), or external (as direct power coming into the chip). This distinction also relates to the boundaries of the device under-test and the testbench.
• The values of power rails can be a fixed voltage, a range of voltages, or possibly switched off. Note that “off” is different from “zero volts”—a 0V rail still acts as a voltage source, whereas an “off” supply doesn’t source or sink current, and can have its voltage affected by adjacent nets. Figure 1 shows leakage from an “on” rail to an “off” rail.

Figure 1. Inter-domain leakage from an “on” domain into an “off” domain.

• Unified Power Format (UPF) states describe the values, states, and connections for power rails, switches, and isolation. A circuit design can be checked either with or without an accompanying UPF state description. UPF can eliminate false positives, for example, by forcing two power rails to track at the same voltage. Checking a circuit without its UPF description may yield many false positives that would be eliminated by taking the UPF information into consideration.

As circuit size increases, circuit complexity and risk also increase, but so does the number of “don’t-care” results, as shown in figure 2.

Figure 2. Test multiplexers are a common source of false violations in traditional ERC checks.

Traditionally, verification has been left until the later stages of the design process, but this approach can result in costly and time-consuming rework as issues are discovered much later in the flow.

Embracing the shift-left mindset

To stay ahead of the curve, you can deploy a newer electronic design automation (EDA) tool that integrates leakage and reliability verification into the pre-layout stages to identify and address potential issues before they become larger problems. This “shift-left” mindset not only saves time and resources but also helps to ensure that the final product meets the highest standards of quality and reliability. Figure 3 shows a screen capture of the Siemens Insight Analyzer graphical user interface showing how analysis results are viewed.

Figure 3. Adopt a shift-left mindset with Insight Analyzer to catch issues early in the design process.

Siemens designed this early leakage analysis tool to tackle leakage issues head-on. Using advanced algorithms, the tool can quickly and accurately identify the risk of leakage between power domains, as well as a host of other circuit reliability issues. The tool takes a holistic view of the circuit and its functionality, automatically recognizing structures like logic gates, latches, current mirrors and level shifters to help it understand the big picture. This allows the tool to quickly and accurately identify the risk of leakage between power domains, as well as a host of other circuit reliability issues that may be missed by simulation alone. This level of circuit analysis is crucial, as even the most subtle of circuit changes can have a profound impact on the overall quality and reliability of the design.

Checking for leakage with the Insight Analyzer tool

The problem of power domain leakage can be viewed from multiple perspectives. Depending on the type of problem, and the circuit structures involved, leakage might be easily identified from one analysis, but invisible from another. The Insight Analyzer tool from Siemens EDA contains a rich set of built-in checks for circuit reliability issues, including floats, over-voltage and many other circuit issues that can’t always be caught by simulation. At the simplest level, the relevant checks for leakage between power rails are the contention and domain leakage checks.

The contention check evaluates conflicting power switch controls. The software traces the path of the control logic “upstream” from each power switch to determine which rails will be on, and at what voltages. In this check, the point of view is the controlling logic of the switches.

Figure 4 shows a high-level view of a rail contention situation. Multiple power rails can be used to supply power to the same circuit. If their control logic is not adequately exclusive, they could be in a state where the two rails are directly connected to each other. In this case, the Insight Analyzer tool traces “upstream” to find the origin of the Enable1 and Enable2 signals, and reports a violation if there is any chance that they could both turn on simultaneously.

Figure 4. In power rail contention, VDDA and VDDB both supply power to the circuit. If their enable signals can signals can be switched on together, a direct path forms between the rails.

The domain leakage check searches for parasitic body diodes that could be the root cause of a leakage current, where current from one rail may sink into another rail that is off or at lower voltage. The domain leakage check uses an intelligent “broad scattering” approach to follow all possible unique paths the leakage current could take, without being redundant.

Figure 5 shows a situation reported by the domain leakage check. The Insight Analyzer tool returns a very specific violation, including: the name of the pass gate (also often called a transmission gate) instance, all steps in the leakage path, voltage values, and power states (if applicable).

Figure 5. Inter-domain leakage where a backup power supply powers into a main supply that is turned off.

Contention and domain leakage checks both report on a larger set of different, but related, violations. For example, the contention check reports on rail contention, but also reports contention between power and ground, as well as “crowbar” situations (low-resistance path between power rails).

The STMicroelectronics experience: a case study

You can see the power of tools like Insight Analyzer in real world applications. One such example is the experience of STMicroelectronics, a leading semiconductor manufacturer.

In a paper presented at the Siemens EDA User2User conference, the STMicroelectronics team shared their journey in detecting and addressing high impedance (HiZ) net issues in their designs. The team recognized that while HiZ nets are often seen as problematic, the reality is more nuanced. By understanding the context in which a circuit is used and the local biasing of the circuit, they were able to better comprehend the true nature and degree of concern.

Insight Analyzer played a crucial role in this process, allowing the STMicroelectronics team to increase the coverage of their verification efforts. The team praised the tool’s ease of use, noting that their users were able to become operational within just a few hours of first using it.

Conclusion

As semiconductor technology continues to grow in complexity and scale, leakage mitigation has become an ever-present challenge for circuit designers. Many leakage issues simply can’t be caught through simulation or visual inspection alone. Identifying inter-domain leakage between different power rails is particularly tricky.

Taking a shift-left approach with a dedicated early analysis tool lets you run full-chip, transistor-level, inter-domain leakage identification and correction, ultimately improving design reliability, performance and quality.

Category: Siemens

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