Welcome to the world of Siemens Hardware Assisted Verification (HAV) engines, a fast-paced verification ecosystem that synthesizes the design and a large part of the testbench and then maps it to the Veloce Hardware. This setup runs 1000 to 10000 times faster than a simulator. Roughly, the same design that took days and weeks now runs in minutes. That’s incredible, isn’t it?
A verification environment typically has a design under test (DUT) surrounded by verification-driven constructs. No synthesis tool can synthesize every supported keyword. Design engineers are always careful with limiting themselves to using synthesis-friendly constructs. Verification engineers are more fluid because they do not worry about synthesis. Emulators are no exception. They can synthesize the design, but the testbench runs on a host machine. The two communicate through interfaces or established standard protocols.
Now, such a system is like a relay race. The slowest player can significantly impact the overall performance. The obvious solution is to assign the shortest lap to the slowest player. Simulators are painfully slow in the relay race of Emulators and Simulators. How do we further reduce the time spent on simulators?
The Siemens Veloce team took a multi-pronged approach to provide a solution.
First, Veloce provides a rich set of Veloce transactor libraries (VTLs) of standard protocols and soft memory models. These VTLs are emulation-ready, geared towards performance, and support plug-and-play. A user simply replaces the simulation Verification IP (VIP) with an equivalent Siemens VTL to migrate a large portion of the design. The VTLs cater to large industry segments such as networking, automotive, storage, video, mobile/smartphone, and 5G, to name a few.
