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 Decoding Formal

Archive for December, 2017

Implementation of an Architectural Formal Verification Methodology by ArterisIP

Tuesday, December 19th, 2017

Chances are you’re probably reading this blog post on a mobile device with the utmost confidence that it is doing what you intend it to do.  As consumers, we place a lot of demands on not only our mobile gadgets but also the rest of our personal electronics.  We want them to perform all sorts of tasks efficiently, accurately, and with minimal power consumption.  All this is, of course, important.  But if you look beyond your own microcosm, you will soon realize that everything electronic these days must meet the same if not much more stringent operational standards.  Today’s electronic systems are embedded in every aspect of our lives from energy consumption to manufacturing to finance to travel and beyond.  Undetected bugs may simply be seen as an annoyance when we experience them in our personal devices, but they can have very profound disastrous effects when we look at the larger electronic ecosystem.

Today’s embedded SoCs that drive the world’s electronic ecosystem are high performance, heterogeneous, and multi-processing systems.  Most of these embedded SoCs are likely to contain multiple caches that share a single memory resource. At a high level, cache coherency means that two caches cannot have the same cache line in a dirty state and that if a cache contains a cache line in a unique state, that line must not be in another cache. In addition, at least one transaction must always be able make forward progress (no deadlock).


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