One day recently, I was considering the varied use models for hardware emulation. It brought back a long-forgotten memory of an evening bowling in New England, where I lived for several years in the ‘80s.

New England has a quaint, little-known (outside of the region) type of bowling called Candlepin. While the play is the same as the more popular form of bowling, the pins are long and narrow, and look a bit like candles. The 10 candlepins are set up in an inverted triangle –– one ball in the first row, two in the second, three in the third, four in the fourth –– and look vaguely as if they’re in “lanes.” This could be a diagram for the verification tool space with most of the available verification tools and techniques in separate and distinct lanes, each with its own function.

Not so with hardware emulation because it’s able to fan cross lanes or boundaries and is multi-functioned. The best example is hardware/software co-verification. Emulation can track hardware bugs from a hardware glitch or software failure or detect software bugs caused by software breakdowns or hardware problems. Its final step is verifying that the hardware has been properly designed to run the software.

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The 2015 DVCon/Europe was held in Munich at the Holliday Inns City Center Hotel November 11-12. November in Munich brought back long ago memories of a snow covered city with freezing temperatures when I lived there in the 80s. Not this November. Warm, sunny days crowned the conference and invited attendees to take a 20-minute stroll across the Isar River to Marienplatz, the heart of the city.

2015 was the second year of the conference. For the enjoyment of Accellera, the sponsor of the event, it recorded an increase in attendees (from 220 to 270) and in exhibitors (25). The success was achieved despite a Lufthansa’s attendant strike that prevented about 50 people from attending and the simultaneous running of the popular Productronica Conference in Munich and ARM TechCon in U.S.

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Graphics chips, the longtime champs of massive designs, have lost their title to the new heavyweight, Ethernet switch and router chips, which weigh in at half a billion or more ASIC-equivalent gates.

The complexity of the networking chip stems from a set of unique characteristics such as large number of ports, expanded throughput, decreased latency, and improved security to assure fewer network failures and collisions when packets are transmitted simultaneously.

Just consider the verification plan of a recent Ethernet switch SoC design with a 128-port interface and a variable bandwidth of 1/10/40/100/120Gbps. The project team decided against using an HDL simulator, the traditional and most popular verification tool.

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Recently, I read a quote from Peter G. Davis from The New York Times in 2007, who wrote: “’Cosi` fan tutte’ was virtually unknown a half-century ago, considered a trivial farce scarcely worth reviving. Now it is admired as one of Mozart’s most profoundly ambiguous and psychologically disturbing stage works.”

With due differences in subject matter – classic opera versus chip design verification – and, in a judgement call, a trivial farce versus expensive and hard to use, I see a similarity with what’s happening with hardware emulation.

First devised in the middle of the 1980s, driven by the progress in field programmable gate-array technology, hardware emulation had a very difficult time to be accepted, and for good reasons. Not only it was very expensive to purchase, it was also atrociously unfriendly to be deployed. Only pioneering engineering teams –– dealing with very large designs that were processors and graphics back then–– had the stomach (and deep pockets) to adopt such technology.

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Many PBS stations in the U.S. are promoting the rebroadcast of the 1984 series “The Jewel of the Crown.” A jewel in the crown was my sentiment about the recent DVCon India, one of several design and verification conferences organized by the industry standards organization Accellera Systems Initiative.

DVCon India was held in Bangalore September 10-11. With an attendance of 650 versus 400 in 2014, it was held in the Leela Palace, a significantly larger venue than last year’s Hotel Park Plaza.

All in all, it was a great conference, full of substance information and great people in an attractive facility, if one can overlook the road traffic. It reminded me of a Circle of Hell from Dante Alighieri’s 14th-century poem, “Divine Comedy.”

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