Recently, I read a quote from Peter G. Davis from The New York Times in 2007, who wrote: “’Cosi` fan tutte’ was virtually unknown a half-century ago, considered a trivial farce scarcely worth reviving. Now it is admired as one of Mozart’s most profoundly ambiguous and psychologically disturbing stage works.”

With due differences in subject matter – classic opera versus chip design verification – and, in a judgement call, a trivial farce versus expensive and hard to use, I see a similarity with what’s happening with hardware emulation.

First devised in the middle of the 1980s, driven by the progress in field programmable gate-array technology, hardware emulation had a very difficult time to be accepted, and for good reasons. Not only it was very expensive to purchase, it was also atrociously unfriendly to be deployed. Only pioneering engineering teams –– dealing with very large designs that were processors and graphics back then–– had the stomach (and deep pockets) to adopt such technology.

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Many PBS stations in the U.S. are promoting the rebroadcast of the 1984 series “The Jewel of the Crown.” A jewel in the crown was my sentiment about the recent DVCon India, one of several design and verification conferences organized by the industry standards organization Accellera Systems Initiative.

DVCon India was held in Bangalore September 10-11. With an attendance of 650 versus 400 in 2014, it was held in the Leela Palace, a significantly larger venue than last year’s Hotel Park Plaza.

All in all, it was a great conference, full of substance information and great people in an attractive facility, if one can overlook the road traffic. It reminded me of a Circle of Hell from Dante Alighieri’s 14th-century poem, “Divine Comedy.”

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