Hardware-Assisted Verification Evolves in 2023 – Siemens

By Jean-Marie Brunet, Vice President and General Manager, Siemens

Jean-Marie Brunet

Rapid adoption and revenue growth in the hardware-assisted verification market segment was especially apparent in 2022 as verification and validation costs soared, a result of IC/SoC complexity. Justification for hardware-assisted verification tools was not questioned.

Moving into 2023, everything indicates a continued trend. The year bodes well as hardware-assisted verification solutions become more fully integrated into verification and validation environments while serving two distinct parallel tracks. One track is hardware and the other is software.

The hardware track plays to hardware designers who want hardware-assisted verification solutions to address three significant challenges. The first being hardware emulation for compilation and debug of large, 12-billion gate or more designs.

The second being emulation offload where FPGA-based hardware complements emulation for a well-defined purpose. To run faster and reduce the cost per verification cycle. The key is to maintain a common verification environment for both and deliver congruency in set up and results for the verification and validation tasks.

The third is traditional prototyping, a use mode with close-to-at-speed peripherals, and again, a common verification environment with emulation and offload. In both emulation offload and traditional prototyping, workload acceleration is needed to run real live software workloads.

The ability to run software workloads across different types of hardware with a consistent environment looks like a reality in 2023, as does the goal to efficiently run/execute within a unified verification and validation environment. In addition, to move fluidly between the IP and the system stages at multiple levels of abstraction, which allows complete verification and validation of all aspects of the SoC.

About Jean-Marie Brunet

Jean-Marie Brunet is the Vice President and General Manager for Hardware-Assisted Verification at Siemens EDA. He has served for over 20 years in application engineering, marketing, and management roles in the EDA industry, and has held IC design and design management positions at STMicroelectronics, Cadence, and Micron among others. Jean-Marie holds a master’s degree in electrical engineering from I.S.E.N Electronic Engineering School in Lille, France.

Category: Predictions

This entry was posted on Wednesday, January 18th, 2023 at 12:59 pm. You can follow any responses to this entry through the RSS 2.0 feed. Both comments and pings are currently closed.