Among what we observed is that SoC Design should be oriented to be seen as a commodity. A strong demand around SoC Compilation is occurring especially at front-end level. Several major semiconductor companies confirmed that first versions of SoC should be available “at the glance”.

Accelerating the process of SoC creation requires that EDA design tools provide a much higher degree of automation to manage design information very early in the design process. We believe it requires a unique way to manage unified design formats. All design information, including functional design (RTL), architecture (IP-XACT), timing constraints (SDC), power intent (UPF), physical (LEF/DEF), must be taken into consideration together and as early as possible in the SoC build process.

In practice, such approach should allow non-domain experts to make important design decisions. For example, a CAD engineer or RTL designer would have the capability to build a first SoC configuration from design assembly to synthesis.

A complementary trend that we observe is in the design space exploration. Traditional SoC integration approaches are not sufficient anymore to forecast the best PPA design configuration. Given aggressive design schedules and low-cost requirements, the amount of engineering resources required to run multiple what-if scenarios manually may be excessive, preventing design teams from achieving optimized solutions. Industry is looking for automated ways for SoC design planning. Learning algorithms are certainly important direction to take. Current EDA initiatives around ML algorithms are still timid in comparison to other industries, such as robotics and health care.

Bastien Gratréaux, Project and MARCOM Lead at Defacto Technologies

Owner of a master’s degree in management and communication linked to an electrical engineering background, Bastien is leading the communication at Defacto along with close interaction with R&D team for 8 years.

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