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 State of EDA

Archive for September, 2009

Rajeev Madhavan says efficiency is not enough

Friday, September 25th, 2009

When I started these interviews at DAC my first was with Rajeev Madhavan of Magma where we discussed where EDA has gone wrong, along with the perceived controversy over Magma’s finances.  I wasn’t expecting to wrap up this series with Rajeev again until I listened to his keynote at the EE Times Virtual Conference on SoC design.  In his address were two items that made my ears pick up: the fact that the cost of designing SoCs has gone beyond the potential for profit and that drastic changes have to be made in the way the industry does business.  In our discussion, he flat out said that EDA tools need to give semiconductor companies the ability to reduce headcount, not just make engineering staff more efficient.  Bold words and maybe a bold vision for EDA. Here’s the interview.

This is an unsponsored podcast from New Tech Press

Gary Smith Sees the glass more than half full

Thursday, September 24th, 2009

After I finished meeting with EDA companies at DAC, I sat down with Gary Smith of GarySmithEDA to talk about how DAC went and where he saw the industry going.  Gary has long been an advocate of Electronic System Level design methodology and has said it was the coming thing for many years.  He still sees that to be true, but no sees it as crucial for the survival of the industry now.  He expects customers will come back to DAC in larger numbers once the industry decides to focus on ESL and de-emphasizes RTL.  He also warned that startups still focused on RTL tools may not survive long enough to make the next DAC. Here’s the interview.

This is a non-sponsored podcast from New Tech Press

Docea Power: It’s still just about efficiency

Thursday, September 17th, 2009

Ghislain Kaiser, CEO of Docea Power was my last vendor interview at DAC and one of my favorites because, well, he’s a new face in EDA and he has such a great name.  It’s nice to see someone other than the usual suspects.

Docea tools help designers explore low-power architecture, with a focus on hardware/software partitioning and “support of the modern and powerful power management techniques,” whatever that means. It’s a cool technology and addresses a significant issue in engineering efficiency for SoC design.

Unfortunately, Kaiser was not able to give me a hard, bottom line accounting of what the tool does for profitability.  It’s still just about the engineer and not the bottom line. Here’s the interview.

Lynguent CEO focuses on efficiency

Friday, September 11th, 2009

My search for financial significance in EDA took me to Dr. Martin Vlach, CEO of Lynguent.  Their website states that:

“Lynguent was created because we believed we can improve your AMS design flow, improving your productivity and reducing overall engineering and manufacturing costs.”

Talking to Dr. Vlach you know you’re talking to a guy who knows his technology and that it provides value to customers.  When pressed, however, he said the actual monetary significance of their product was “beyond what he thinks about.”  He cares about making engineers efficient, which is a great thing.  But it doesn’t help the CFO much. Here’s The Interview.


Silicon Frontline hits the bottom line

Thursday, September 3rd, 2009

OK, NOW we’re talking.  I talked with Dermott Lynch, vice president of marketing for Silicon Frontline Technology about the company’s parasitic extraction technology and got the usual pitch about what was obviously a very innovative product.  That’s what you come to expect from an EDA startup: great technology.  Then I asked the question no one likes.  I asked how much this tool meant to the bottom line for a fabless company.  AND I GOT AN ANSWER!  Could have knocked me over with a balled up sock.  The Silicon Frontline tool shears off more than 5 percent of the cost of bringing a new chip to market.  When the minimum cost of making a new chip is $50 million, that is significant.  Well done, Dermott. Here’s the link to the interview.

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