IP Showcase 
Peggy Aycinena
Peggy Aycinena is a contributing editor for EDACafe.Com Flex Logic & TSMC: embedded FPGA cores on 16nm FinFETsDecember 14th, 2016 by Peggy Aycinena
In a phone call to discuss the announcement, Flex Logic CEO and Co-founder Geoff Tate was clearly ebullient: “Last August we were talking about TSMC’s 40-nanometer ULP, ultra low power, and now this week we’re talking about the first 16-nanometer finFET plus. “This one, our EFLX 100, is like the one we announced at 40 nanometers – but at 16 nanometers it will run much faster! “We’ve done extensive measurements [to confirm] for many applications that these cores will run at 1GHz or faster, even in worst-case temperature conditions.” Read the rest of Flex Logic & TSMC: embedded FPGA cores on 16nm FinFETs IP Design Challenge: efabless & X-FAB promote Ingenuity, February deadlineDecember 7th, 2016 by Peggy Aycinena
What they’re looking for are IP designs applicable to an ultra-low power voltage reference, and the companies are willing to make it worth your while. If your design is one of the top three selected, you’ll receive a monetary award and your IP will be made available to a global customer base through both X-FAB’s IP web portal and efabless’ online marketplace. Best of all – you’ll hold onto all rights for your submission. Read the rest of IP Design Challenge: efabless & X-FAB promote Ingenuity, February deadline REUSE 2016: Addressing the Four FreedomsNovember 24th, 2016 by Peggy Aycinena
There are four major issues that haunt the IP industry, four freedoms demanded by the diverse, global customer base that buys from the IP industry. If REUSE 2016 wants to become the forum for those who provide IP to those customers, all four of these issues need to be addressed on December 1st in one way or another. Ridgetop Group & BaySand: Whole greater than Sum of PartsNovember 17th, 2016 by Peggy Aycinena
Together the companies say they will “work cooperatively to develop a series of new applications to increase their existing mixed-signal IP portfolios.” Considering the growing emphasis on IP in the semiconductor supply chain, this news is of particular interest. The implication being IP companies need to provide design services to succeed. Ridgetop Group is an IP company, BaySand a design company. Together they provide what the market needs, good IP and design services tailored exactly to the system integration profile of a particular class of IP. Read the rest of Ridgetop Group & BaySand: Whole greater than Sum of Parts DAC 2017: Deadlines for IP Submissions start November 15thNovember 10th, 2016 by Peggy Aycinena
[NOTE: The December 14th date listed above is for invited Design Track & IP Track proposals. All other proposals for DAC 2017 Design Track & IP Track content can be submitted for review up until January 14, 2017. Thank you to DAC Press Chair Michelle Clancy for this important clarification.] In other words, if you want to present within the IP Track at the 54th Design Automation Conference, you need to get going now. The committee that will be overseeing review of these proposals is being headed up by Lattice Semiconductor’s Claude Moughanni – his group taking seriously their role in assembling an IP program that’s both informative and cutting edge. Moughanni’s committee members include IPnest’s Eric Esteve, Synopsys’ Marc Greenberg, ARM’s Simon Rance, Freescale’s Henning Spruth, Mentor’s Farzad Zarrinfar, Intel’s Ty Garibay, Samsung’s Kelvin Low, Silvaco’s Warren Savage, and Cadence’s Karamveer Yadav – an impressive group who are indeed subject experts. So, why should you go to all the effort to submit something for review by this group? Is there really any benefit in taking the time to participate at DAC, next year or ever? Read the rest of DAC 2017: Deadlines for IP Submissions start November 15th REUSE 2016: Glamor Touches IP, at lastNovember 3rd, 2016 by Peggy Aycinena
“REUSE 2016 is the first of an annual conference and trade show to bring together the semiconductor IP supply chain and its customers for a full day of everything to do with semiconductor IP. Hosted in the heart of Silicon Valley at the world-famous Computer History Museum, there could not be a more appropriate venue for a day focused on the hottest segment of the semiconductor industry.” EDA Death Spiral: Qualcomm/NXP last nail in coffinOctober 27th, 2016 by Peggy Aycinena
Yes, happy for investors that Qualcomm is buying NXP, but the end result will be a nasty one for technical innovators in EDA. Yet another reduction in the number of customers for EDA tools. Not necessarily a reduction in the number of seats, but a reduction in the number of actual separate corporate entities looking for tools for chip design. Of course, for those who love large, lumbering organizations with almost as many people in the typing pool as in the engineering pool – more consolidation is great news for the semiconductor business and for the electronic design automation business, as well. However, for those who still remember when EDA was a Wild West full of crazy startups, wacky business ideas, and loads of shifting sands between a constantly morphing/re-morphing population of EDA startups and an also-always morphing/re-morphing population of chip-design customers – take note: Those days are gone. Forever. Read the rest of EDA Death Spiral: Qualcomm/NXP last nail in coffin DVCon Munich: IP Integration, Automotive, Smart Cities, System DesignOctober 13th, 2016 by Peggy Aycinena
It’s a tiring trip from Silicon Valley to Bavaria, but the quality of these presentations, combined with the rest of the content at DVCon Europe, will make the trip well worth the effort. Hope you’re going. Read the rest of DVCon Munich: IP Integration, Automotive, Smart Cities, System Design The Tate Effect: Confidence in Flex Logix Team & TechnologySeptember 22nd, 2016 by Peggy Aycinena
When Tate and I spoke by phone recently, he offered the Flex Logix elevator pitch, and then focused on the company’s August press release. “We are like the ARM of FPGA,” Tate said, and then laughed. “No, we are not expecting to be acquired by SoftBank anytime soon.” “However, ARM was the first to successfully embed processors,” he said, “and at Flex Logic we are [doing that] with FPGAs.” Read the rest of The Tate Effect: Confidence in Flex Logix Team & Technology IP Theft: Cheaters & Chuckles vs. Chalk & CheeseSeptember 15th, 2016 by Peggy Aycinena
Kelly said Synopsys earns about $200 million per year selling IP, and loses another $100 million to theft. Cheaters are a real problem, he lamented, and as Director of License Compliance for Synopsys he should know. Kelly did not have the floor to share these laments, however, until Warren Savage, GM of IP at Silvaco, opened the meeting. Speaking from the podium as moderator of the evening’s discussion, Savage said the real problem is the bumblers, those designers and companies who lose track of licensing obligations for IP that was either purchased some time ago, or was brought into the design effort on a data stick fished out of the pocket of someone who’s joined the organization through a poorly managed M&A. In other words, when Chuckles the Clown uses IP, often as not he doesn’t realize some monies are owed to the third-party IP vendor who created it in the first place. Savage offered this statistic: On an average SoC today, there are 150 to 200 blocks of IP, but only a small percentage of those blocks are actually paid for. Read the rest of IP Theft: Cheaters & Chuckles vs. Chalk & Cheese |
|
|
|
||||||
|
|||||||
|
|||||||
