Guest Blogger 
Lu Dai
Lu Dai is Chair of Accellera Systems Initiative and Senior Director of Engineering at Qualcomm where he leads front-end methodology and SOC design verification. In this role, he oversees front-end design and verification methodology initiatives and leads SOC design verification execution. He … More » Make an Impact and Get Involved in Standards Development and EvolutionMarch 12th, 2020 by Lu Dai
Semiconductor design and verification professionals use a variety of languages to model and verify their new ideas in this exciting era of 5G, AI, IoT and autonomous vehicles. Taking a step back, it’s important to understand where these design and verification languages came from, because in the early days of IC and system design there were multiple proprietary languages in circulation. Consider some of the following early languages and simulators used to describe and simulate IC designs:
Starting in the 1980s, we began to see two simulation languages take hold commercially: VHDL and Verilog. As the industry adopted standard languages, the task of moving your ASIC design from one foundry to another became much easier, especially as logic synthesis tools like Design Compiler from Synopsys were gradually adopted.
History The Verilog language came from a single company, Gateway Design Automation, but was then donated to the Open Verilog International (OVI) organization; VHDL was defined by VHDL International. Both OVI and VHDL International were started in 1991 as standards bodies, which was a good thing. Fortunately for our industry, OVI and VHDL International merged in 2000 creating Accellera, so instead of dueling language standards groups, there was now a single standards organization to keep Verilog and VHDL coherent and growing. The Superlog language from Co-Design Automation was donated to Accellera in 2002, which then started the definition process for SystemVerilog along with Synopsys donating OpenVera. By 2005 SystemVerilog was adopted as IEEE standard 1800-2005 (now superseded by IEEE 1800-2017). Verilog is a subset of SystemVerilog, and verification engineers often use object-oriented programming in SystemVerilog, which is not synthesizable. Starting in 2006, Accellera formed a Unified Power Format (UPF) technical committee to define how power and power control intent should be described. Accellera then moved the UPF standard over to the IEEE in 2009, and they named UPF as IEEE 1801-2009. Accellera then merged with The SPIRIT Consortium in 2009, bringing in the IP-XACT standard for IP reuse. The Open SystemC Initiative (OSCI) merged with Accellera in 2011, creating Accellera Systems Initiative and bringing in the SystemC language. In 2013 Accellera added the Open Core Protocol (OCP) standard from the OCP International Partnership (OCP-IP). So, yes, Accellera has been quite the dominant standards body for our semiconductor design and verification languages for the past 19 years now. The standardized languages at Accellera are used by both design and verification engineers, and at most large companies these engineers are on separate teams. Design engineers are tasked with writing the requirements for an IC project, then implementing the features by coding in their favorite language. Verification engineers read the requirements and then write tests to verify that all features are in fact functioning to specification; when they find a bug, they then file a report so that the design group can fix the issue or clarify the requirements.
Involvement As a practicing engineer, perhaps you’ve wanted to influence what a language should support. You and your company can do just that by joining a standards committee at Accellera. Take a look at which companies are Corporate members:
There are even more Associate members:
Start-up companies and University members include:
Working Groups All of the technical work for language standards is done through working groups, and here’s where to get started: Each of these working groups has an online forum for discussing and clarifying topics. One of the newest working groups is for Portable Stimulus, started in 2015; its focus is on specifying intent and behavior in a reusable fashion across emulation, simulation and silicon. The Portable Test and Stimulus 1.0 standard was approved in 2018, and version 1.0a was released in February 2019. The working group is currently working on PSS 1.1. The IP Security Assurance Working Group is tackling the security issues when third-party IP blocks are combined together. The working group is focusing on existing standards that pertain to IP specification, design, verification and integration where security risk is a concern, as well as known security concerns that have been identified by either industry experience or security researchers. Formed in 2018, the IPSA Working Group recently released a whitepaper that describes its initial proposal to address the industry’s security concerns involving IP integration. As is the case when we have standards in public review, the working group seeks input and reactions from the community on this whitepaper. Our standards are user-driven and we recently announced a new working group to develop a standard to address Functional Safety. With the growth of ADAS and autonomous vehicle development, I expect that the standardization efforts will have quite a positive impact on our design community. Interested members met for the first time as a Proposed Working Group (PWG) in December 2019 to discuss what might be standardized in the design process for safety critical systems. Accellera’s Board of Directors approved it as the Functional Safety Working group in February. What’s unique in these working groups is that members come from the user community, EDA vendors and academia. PWG’s are open to the community, so anyone can participate in a PWG to share ideas and experiences. Once a PWG is approved as a working group, at that point participants will need to be a member of Accellera to help shape the development of the standard. In addition to the ongoing development of standards among our working group members, Accellera sponsors technical conferences around the globe. It is our goal to foster discussion and provide education on the latest standards developments and advances in the industry to benefit design and verification engineers. Conferences Accellera sponsors four DVCon events each year. Our flagship conference and exhibition is held in Silicon Valley, followed by China, India and Europe. The technical programs of each DVCon conference are targeted toward the needs of the design and verification engineers in that region. Our standards efforts are often the result of discussions at these gatherings. There have been presentations at recent DVCon events addressing the need for AMS extensions for UVM to make UVM more mixed-signal aware. Our recently announced UVM-AMS Working Group is a result of those discussions, many of which were held in Munich at DVCon Europe. We also sponsor SystemC Evolution Day which is co-located with DVCon Europe. It is a full-day technical workshop focused on the evolution of SystemC standards. IEEE and Accellera Some language standards have started in Accellera and then moved into IEEE, such as SystemVerilog, SystemC, UPF and UVM. The IP-XACT standard started out in Accellera, then moved to IEEE, and is now back at Accellera for an update. There is tremendous cooperation between the two standards groups. For example, Accellera sponsors the IEEE Get Program which gives the community access to select standards and documentation at no cost. The Accellera-sponsored IEEE Get Program has resulted in more than 100,000 downloads, providing free access of electronic design and verification standards to engineers and chip designers around the world. Next Steps There are a number of steps to take in your journey to learning more about standards. It could be attending a DVCon conference in your local area, filing a bug report at accellera.com, or even contributing to a standard by joining a working group. You will find many other semiconductor professionals along the way, each contributing to languages in order to make their work tasks easier and get their products out the door quicker with high confidence that first silicon will work without surprises.
Tags: Accellera Category: DVCon |
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