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Stan Krolikoski, Cadence; Dennis Brophy, Mentor; Yatin Trivedi, Synopsys
Stan Krolikoski, Cadence; Dennis Brophy, Mentor; Yatin Trivedi, Synopsys
Stan, Dennis and Yatin have been involved with the promotion of EDA standards for over 10 years.

Accellera at DAC: Defining a Universal Verification Methodology

June 7th, 2010 by Stan Krolikoski, Cadence; Dennis Brophy, Mentor; Yatin Trivedi, Synopsys

First of all, we’d like to invite all the DAC attendees to Accellera’s breakfast and panel about UVM: Charting a New Course on Tuesday, June 15, 7:30 am – 9:00 am, Room 203B in Convention Center.

It is no news when one talks about increasing complexity of designing the SoC devices. It is a foregone conclusion that designing is a relatively bounded problem compared to verification. Just as design reuse through Semiconductor IP (aka design IP) helped bring the designers up the productivity curve, in the last decade Verification IP (VIP) has done the same for the verification engineers. Two leading methodologies, Verification Methodology Manual (VMM) and Open Verification Methodology (OVM), helped accelerate the adoption of structured verification methodologies using SystemVerilog as well as the creation of commercially available verification IP to independently validate integration of design IP in SoCs. Essentially, both methodologies are a collection of SystemVerilog classes with inherent semantics for their behavior in different phases of the simulation. The user creates verification objects from these classes and attaches them to the design components as traffic/data generators, monitors, checkers, etc.

Both verification methodologies are built on SystemVerilog, both have been available under Apache license, and both have been successfully deployed in production environments – with one caveat, as long as the verification IP was built on only one of them and not the other. This is where the problem arises. Many projects acquire Verification IP (VIP) from multiple vendors, and occasionally even multiple groups inside a company may have worked independently using different methodologies. Naturally, there is a conflict for integrating such VIPs into one consistent verification environment.

In 2007-08, this was recognized as an issue, and leading users formed the Verification IP Technical Subcommittee (VIP-TSC) under Accellera. By July 2009, 12 recommended practices were formalized in the form of an API to allow interoperability of VMM and OVM VIPs in a single environment. However, it was only seen as the first step in solving a larger problem – that of having publicly available universal base classes that can be used for creating a wide variety of VIPs. Naturally, if all VIPs are based on the same base class library, one does not need to go through an interoperability API. Thus came to life the second phase of the VIP-TSC efforts, UVM base classes.

The UVM base class is based on SystemVerilog. OVM 2.1.1 was used as the starting point to define UVM. In Accellera’s Early Adopter release of the UVM (UVM-EA), there were some enhancements to Callbacks and End-of-Test features, and a new type of Message Catcher callback was added, along with renaming of objects to UVM_*.The VIP-TSC has a list of items that brings features from OVM, VMM and other home-grown methodologies to add to UVM-EA for release 1.0 and beyond. However, current and planned features of UVM base class can be best described as the reflection of collective knowledge of the verification experts participating in VIP-TSC.

In other words, are we just transferring the knowledge from syntactically and semantically different methodologies into a new one? What is the real value to this exercise? If we fast forward by a year, what would UVM base class release X look like? What features should it have to solve the problems faced a year from now? 3 years from now? Are we looking at adding more of the same or make a quantum leap in our ability to deal with much larger and significantly more complex designs? What specifically are we doing to improve our ability to find bugs in the design and then fix them?

This is the topic of our breakfast discussion at DAC, hosted by Accellera and sponsored by its members Cadence, Mentor and Synopsys. The panelists are verification experts from our user and vendor community. Our moderator is no stranger to challenges and stimulating great dialog across the industry. This is the time for you to find out more and chime in.  See you there.

UVM: Charting the New Territory
When/Where: Tuesday, June 15, 7:30 am – 9:00 am, Room 203B in Convention Center
Host: Shrenik Mehta, Chairman, Accellera
To register visit:
Moderator: Gabe Moretti,
Sharon Rosenberg, Verification Solutions Architect, Cadence
Hillel Miller, Verification Manager, Freescale and VIP-TSC co-chair
Mohamed Elmalaki, Verification Expert, Intel
Tom Fitzpatrick, Verification Technologist, Mentor
Janick Bergeron, Synopsys Fellow, Synopsys
Stacey Secatch, Sr. Staff Verification Engineer, Xilinx

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One Response to “Accellera at DAC: Defining a Universal Verification Methodology”

  1. Adam Sherer says:

    I’ve just got to say that is has been an honor to work with the Accellera VIP TSC team during the development of the UVM. As the secretary of the group I get a more than first hand look at how the standard comes together. The level of cooperation and the drive to deliver the best solution for industry is something that should make us all proud and embodies the EDA360 spirit of raising everyone’s productivity.

    =Adam “Sherilog” Sherer, Accellera VIP TSC Secretary and Cadence Product Management Director

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