Is there a disconnect in your die, package and board design methodology? As technologies evolve to meet demands of higher performance, smaller size and lower cost, there are several challenges in the design of chips, packages and boards which must be addressed with an integrated analysis and verification methodology.

For example, maintaining power integrity means ensuring that the entire power delivery from the voltage regulator on the PCB to the transistor on the die meets the device power supply requirement. This involves designing and optimizing the location of the voltage regulator, PCB and package de-coupling capacitors, power plane impedance, bump placement, on-die power grid, on-die de-coupling capacitors and switching transients in one design and analysis environment. Sufficient data sharing needs to happen between each of the design teams to ensure that the final working part delivers the supply current as needed by the chip within the specified voltage fluctuation limit.

On the other hand, high-speed memory and serial interfaces have very stringent requirements for simultaneous switching noise resulting from their need to maintain the fidelity of the transmitted and received signals. The simultaneous consideration of the IO ring design, IO and decoupling capacitor cell placement, input switching pattern, and package/board power and signal layouts is necessary to meet the goals of near end and far end SSN.

However, as these challenges become increasingly critical to the success of next generation of designs and systems, there is a singular lack of tools and methodologies to address these issues. Multiple disparate techniques exist with contention about the efficacy of each. Tool-sets exist but address only parts of the problem. For example, frequency domain analysis tools employing fast electromagnetic field solvers have looked at the mid and low frequency power delivery network system noise. Hence, time domain analysis tools are needed to solve for the high frequency noise that result from the switching of devices on the chip. But these time domain analysis tools need accurate models of the package and board to provide realistic on-die voltage and current waveform data. Similarly for IO signal integrity analysis, most analysis methods compromise either on the modeling sophistication or on data inclusiveness to generate results in a reasonable time-frame. For example, either the entire IO bank is not considered in the simulation or the signal/power ground network coupling are ignored. These trade-offs however impact the quality of the results which are critical in determining whether the chip-to-chip transmission will happen according to the specifications.

Apache is sponsoring a workshop at DesignCon where several industry experts from semiconductor and system design houses including Larry Smith from Altera, Jim Antonelis from Broadcom, Rick Brooks from Cisco, and Dr. Souvik Mukherjee from Texas Instruments are coming together to discuss their understanding of these challenges, to present the approaches they are taking and to outline the needs they have for tools and methodologies. Additionally, a panel discussion will be conducted to foster discussion on the techniques for chip model creation, package and board extraction tools and co-simulation methodologies. Perspectives on system modeling, extraction and simulation using EM tools, methods of accurate and distributed modeling of the IC and techniques of performing time domain and frequency domain simulations will be shared through presentations addressing both power and signal integrity issues. The topics will include practical methods for designing and evaluating the system performance. Another important topic is to define a method to build confidence in these methods. This workshop will be an open forum to share insights, discuss issues and present proven techniques. Such an open exchange of ideas and information from semiconductor and system companies will help to define the content of future technologies for chip and package modeling and system level verification of power and signal integrity.

I hope you will join us in the workshop “Practical methodologies for Power/Signal Integrity of Chip-Package-Board Designs” held from 9AM to noon on Thursday February 4th at the DesignCon conference in Santa Clara Convention center.

For more information on the workshop, please visit http://www.designcon.com/2010/attendees/th_th1/index.asp

You can also register for complimentary Exhibit PLUS pass to DesignCon for entry to the workshop. http://www.apache-da.com/apache-da/Home/NewsandEvents/Events.html