Cadence Press just introduced a new title on Advanced Verification Topics by Bishnupriya Bhattacharya and contributors.  Here is a small quote from what Adam Sherer, Cadence Product Marketing Director, said in the Preface to the book:

Consumers may perceive that “it’s a digital world,” but these advanced verification topics speak to the magic that goes on under the hood of every SoC. As verification engineering managers and team leaders, we know that MDV, multi-language VIP, low-power, mixed-signal, and acceleration topics are converging at 20 nm and beyond; but we don’t want to create whole new methodologies for each one. The authors of this book realized this, and selected the Accellera UVM standard as the common base from which to offer solutions that leverage reuse and raise team-level productivity. That’s why we have written this book—not only for verification engineers familiar with the UVM and the benefits it brings to digital verification, but also for verification engineers who need to tackle these advanced tasks. Though the solutions in this book are not standardized, most of them are available through open-source code. For all of you, the material in this Advanced Verification Topics book is provided as a means to stay productive and profitable in the face of growing verification complexity.

EDACafe has exclusive previews of the text by clicking on the links below.

Advanced Verification Topics – Preface

Advanced Verification Topics – Table of Contents

Advanced Verification Topics – Ch. 5 Developing Acceleratable Universal Verification Components (UVCs)

You can also see Adam’s interview from DVCon 2012 where he introduces the book right here.

Last week was the Synopsys Users Group Silicon Valley 2012 annual meeting.   On Monday March 26, Aart de Geus, CEO of Synopsys gave an illuminating and heart felt keynote that reflected on where we have come from and where we are going as a design industry.  His mention of meeting Barney Kessel, famous Jazz guitarist, when he was a young man, poignantly told of his respect for the greatness that resides in all of us.  Afterwards, I interviewed Aart about the the keynote.

Read the rest of SNUG 2012 Silicon Valley Video Interviews and Design Community Expo Photos

I had the pleasure of attending the International Symposium on Quality in Electronic Design (ISQED) 2012 held in Santa Clara, March 19-21 at the Techmart.  I took some photos at the event.  See if you can spot Georgia Marsalek of ValleyPR in any of the pictures.

Enjoy!

The Common Platform Technology Forum 2012 took place at the convention center in  Santa Clara, CA on March 14th.  The Common Platform is an alliance of Samsung, IBM and GLOBALFOUNDRIES to deliver foundry services using the same silicon platform.   I had the pleasure of listening to the Keynote addresses in the morning and visit the Partner Pavilion in the afternoon to see all the ecosystem partners for the Common Platform.  Since it was “PI day” (3/14), we enjoyed pie-on-a-stick at break time between program events.   You can see what that looks like in the photo gallery below.

Follow the links to listen to each of the Keynotes:

Dr. Gary Patton, Vice President of Semiconductor Research and & Development Center, IBM spoke on  “Is Scaling Over? or Is there a Future in Silicon and Beyond?”

Subramani Kengeri, Head of Advanced Technology Architecture, Office of the CTO, GLOBALFOUNDRIES spoke on “Winning Together – Driving Innovation through Strategic Collaboration”

Dr. Jong Shik Yoon, Senior Vice President of Semiconductor R&D, Samsung spoke on “3D Device Technologies – Opportunities and Challenges”

Simon Segars, Executive Vice President and General Manager, Physical IP Division, ARM spoke on “Collaborative Scaling to 14nm and Beyond”

Read the rest of Common Platform Technology Forum 2012 – Listen to 4 Keynotes and Enjoy Partner Pavilion Photos

Cadence held their CDNLive! 2012 Silicon Valley event at the DoubleTree Hotel in San Jose, CA on Mar. 13 and 14.   I had the pleasure of hearing two keynotes by Rick Cassidy, President of TSMC North America and Tom Lantzsch, Exec VP of  Corporate Development at ARM.  Both addressed the growing challenges and opportunities for the next generation of low-power smart devices that will be coming in the future but from two different angles:

“CDNLive Keynote: The Silicon Century and the Future Ahead”, Rick Cassidy, Pres. TSMC N.A.

“CDNLive Keynote: The Future of Smarter Systems, Apps, Internet of Things”, Tom Lantzsch, Exec. V.P. Corp. Development, ARM

I also spoke with Rod Simon from OpenText who was exhibiting at the Design Expo. He was presenting their secure high-speed remote connectivity product and a new MS-Outlook plug-in for huge file transfers that is secure and trackable.  Follow this link to hear this 4 min.  interview:

“Exceed onDemand and New Managed File Transfer”, Rod Simon, OpenText Connectivity Solutions Group

I also took photos at the Design Expo.  Enjoy! Read the rest of CDNLive! 2012 Silicon Valley – Two Keynotes, an Interview and Photos

I was at DVCon 2012 in San Jose, CA, and did over 25 video interviews at the event with different exhibitors, analysts such as Gary Smith, and industry colleagues such as Mark Gilbert of EDA Careers and Ali Iranmanesh of the International Society for Quality Electronic Design.   I also was on the ‘receiving end’ of some questions, when Ed Lee of LeePR graciously took the time to ask me about the state and future of EDA, EDA PR and EDACafe.com.  It was a great event, with a lot of traffic, new exhibitors, and growing attendance.

You can see all of the DVCon 2012 videos here.

Also at DVCon 2102,  I took photos of the booths and exhibits, which you can see below. Read the rest of Design and Verification Conf. 2012 – Videos, Pictures, and I predict the future

I had the pleasure of speaking with Herman Chu, General Chair, SEMI-THERM Conference that is taking place at the DoubleTree Hotel,  March 18-22, in San Jose, CA.   Herman talked about the inflection point we are undergoing right now with thermal demands of electronic systems, and how the SEMI-THERM conference will address those challenges.

You can hear the interview with Herman Chu here.

This DAC blog is from March 2, 2012 by Paul McLellan

 

This year’s CEO forecast panel was held at Silicon Valley Bank. Bankers live better than verification engineers, as if you didn’t know, based on the quality of the wine they were serving!

This year the panellists were Ed Cheng from Gradient, Lip-Bu, Aart and Wally (and if you don’t know who they are you haven’t been paying attention) and Simon Segars of ARM (not their CEO, of course). Ed Sperling moderated. Somebody had managed to dig up the fact that at the start of his career he’d been a crime reporter, so that made sure that we only got truthful answers all evening!

Read More

At DesignCon 2012, I had the pleasure of speaking with Vic Kulkarni, Senior Vice President & General Manager of Apache,  about the issues surrounding the Power Gap in product design.  I also spoke separately with Larry Williams from ANSYS and Aveek Sarkar from Apache Design, Inc. which was acquired by ANSYS in Aug. 2011.

The acquisition of Apache complements ANSYS’ software solutions by bringing together best-in-class products that drive ANSYS’ system vision for integrated circuits, electronic packages and printed circuit boards. The complementary combination is expected to accelerate development and delivery of new and innovative products to the marketplace while lowering design and engineering costs for customers.

To understand the issues around the Design Power Gap and how Power Artist from Apache can help  listen to the interview below.

Read the rest of Addressing the Design Power Gap and ANSYS / Apache Product Roadmap and Integration

I spoke with Todd Westerhoff of SiSoft about their new Virtual Prototype Analysis that can  simulate large systems with thousands of serial links at DesignCon 2012.  You can see the video interview here and below is a short description and link to a technical paper that described the analysis of such a large system.

While not long ago systems had only several serial links, it’s now becoming common for systems to include hundreds – and even thousands – of such links. This paper describes the development and analysis of a large system with thousands of serial links. Due to the system’s size and complexity, the design team invested in a multi-year effort to build and qualify a virtual environment capable of both verifying connectivity and simulating any and all of the channels. Problematic channels with incomplete system-level connections, poor eye openings, or high BER are quickly identified. Performance limiters such as inherent discontinuities (and their associated resonances), and Tx/Rx equalization imbalance are found and examined in detail. The virtual system is also used to guide design choices such as layer stacking, via construction, back-drilling, and trace/connector impedances. Processes to optimize and select equalization choices are also described.

Click here to read Simulating Large Systems with Thousands of Serial Links.

Click here for more information on Virtual Prototype Analysis.