I was speaking with experts at Mentor about the latest developments in back-end physical verification (PV) and design-for-manufacturing (DFM).  It prompted me to take a look at what has changed and what will be essential going forward. Here is what I see for this critical area for IC implementation.

First, we have passed the 28nm barrier and are already looking to a new generation of design. Leading-edge design starts are now at 20nm and we will see production silicon for that node by early 2013.  However, in a new research brief, “Driving first-time silicon success across the IC ecosystem,” by Dr. Handel Jones, semiconductor analyst at IBS, the total number of design starts is not growing.  While System integrators such as Samsung and Apple, are furiously growing their mobile businesses, the ability to integrate ever-larger collections of IP in their SOCs means they do not need to include more ICs in their phones to expand the features of their products.  It is also true that 20nm designs have a much higher NRE than previous generations.  Naturally, this economic incentive will keep some design starts at the 28nm and larger nodes.

Read the rest of The Measure of Nanometer Silicon Success

Calypto has just published a new report on trends in the area of low power design, based on an independent, global RTL power analysis and optimization survey. The survey was executed in late 2011 and had 744 SoC, IC, and FPGA design professionals respond; this report will analyze the survey results and identify relevant year-to-year trends.

By analyzing this comprehensive feedback from design engineers and engineering management, we can better understand the effort spent on reducing power consumption in the design cycle, as well as the popular low power techniques being applied. This becomes especially critical with scaling technology nodes to 65 nm and beyond.

The topics covered in this report are:

1. Survey methodology and demographics
2. Top methods used to reduce power
3. Percent of engineering time spent meeting power specifications
4. Top criteria for selecting RTL power optimization tools
5. Process nodes where RTL power optimization becomes important
6. Plans to implement power optimization tools in 2012
7. Conclusion

Click here to see the Low Power RTL Report.

In a design ecosystem increasingly influenced by software and systems development, massive verification demands, and the boundaries of physics, engineers have a wonderful new set of problems to solve! Yet the principles they will use to innovate their way to exciting solutions and products remain as fundamental and universal as the reality of the Golden Ratio itself. With the aid of some of these principles, Aart talks about what new strategies and methodologies semiconductor players will need to achieve the critical mass necessary to craft productive and creative solutions within a design ecosystem complexity that surpasses anything seen yet in human history.

Click on the graphic to view the video.

Dr. Aart de Geus CEO & Chairman of the Board Synopsys

The technical paper presentation from the Verification conference DVCon 2012 are now available online at the DVCon web-site.  You can them listed here below.

Use the BACKSPACE key to return to the main menu after drilling down into any of the sessions.

Pop-ups must be enabled to view any of the papers or slides.

The importance behind secure and fast file transfer plays a huge factor as it relates to the productivity within an engineering design workflow. Design engineers and semiconductor companies need to boost team collaboration through fast and secure content sharing around the globe to get their designs finalized and onto the chip manufacturer for creation.

Learn how to optimize the engineering design workflow and send your LARGE files faster with this new whitepaper:

Solving Engineering File Transfer Problems: Two Different Days in the Life of an Engineer

There were 8 Best Technical Paper award winners at DesignCon 2012 Jan. 30 – Feb. 2, 2012 across 5 categories.   You can see the winners for each category by clicking on the link below.

Board and System Design Category

•  “Design and Characterization of the Power Supply System for a High Speed 1600 Mbps DDR3 Interface in Wirebond Package”
• Ralf Schmitt, Rambus Inc.; Hai Lan, Rambus Inc.

High-Speed Design Category

•  “A Zero Sum Signaling Method for High Speed, Dense Parallel Bus Communications”
• Chad M. Smutzer, Mayo Clinic; Robert W. Techentin, Mayo Clinic; Michael J. Degerstrom, Mayo Clinic; Dr. Barry K. Gilbert, Mayo Clinic; Dr. Erik S. Daniel, Mayo Clinic

•  “Enhanced Equalization and Forward Error Correction Coding Technologies for 25+Gbps Serial Link System”
• Cathy Ye Liu, LSI Corporation; Pervez Aziz, LSI Corporation; Adam Healey, LSI Corporation

Interconnect Design and Test Category

•  “A Comparison of 25 Gbps NRZ & PAM-4 Modulation Used in Legacy & Premium Backplane Channels”
• Adam Healey, LSI Corporation; Chad Morgan, TE Connectivity

•  “Design Optimization for Minimal Crosstalk in Differential Interconnect”
• Beomtaek Lee, Intel Corp.; Xiaoning Ye, Intel Corp.; Raul Enriquez, Intel Corp.; Kai Xiao, Intel Corp; Ted Ballou, Intel Corp.; Jimmy A Johansson, Intel Corp.

Power and RF Design Category

•  “Are Power Planes Necessary for High Speed Signaling?”
• Suzanne L. Huh, Intel Corporation; Madhavan Swaminathan, Georgia Institute of Technology

•  “Miniaturization of Common Mode Filter Based on EBG Patch Resonance”
• Francesco de Paulis, University of L’Aquila; Bruce Archambeault, IBM;  Muhammet Hilmi Nisanci; Sam Connor, IBM; Antonio Orlandi, University of L’Aquila

Chip-Level Design Category

• “Full System Channel Co-optimization for 28Gb/s SerDes FPGA Applications with Stacked Silicon”  (no URL available)
• Namhoon Kim, Xilinx, Inc.; Daniel Wu, Xilinx, Inc.; Jack Carrel, Xilinx, Inc.; Joong-ho Kim, Xilinx, Inc.; Paul Wu, Xilinx, Inc.