Sanjay Gangal Sanjay Gangal is a veteran of Electronics Design industry with over 25 years experience. He has previously worked at Mentor Graphics, Meta Software and Sun Microsystems. He has been contributing to EDACafe since 1999.
In an enlightening conversation with Dr. Lawrence Pileggi, Coraluppi Head and Tanoto Professor of Electrical and Computer Engineering at Carnegie Mellon University (CMU) and the 2023 recipient of the prestigious Phil Kaufman Award, we delved into a journey that bridges decades of innovation in electronic system design. The Phil Kaufman Award, established to honor the legacy of an industry pioneer, recognizes individuals for significant impacts in technology innovation, education, mentoring, and leadership within the electronic design community.
Dr. Pileggi’s foray into the realm of semiconductors was not a straightforward path. Coming from a background where he was the first in his family to attend college, his intrigue in engineering sparked from a blend of academic strength in mathematics and a personal interest in electronics as a hobby. The semiconductor boom of the mid-1980s further captivated him, setting the stage for a career that would influence the trajectory of chip design and electrical engineering education.
In the ever-evolving world of artificial intelligence, performance and efficiency are paramount. The ability to train and deploy AI models quickly and cost-effectively has become a competitive advantage for organizations across various industries. Intel, a pioneer in the field of semiconductor technology, continues to push the boundaries of AI performance with its Intel Gaudi2 accelerator and 4th Gen Intel Xeon Scalable processors. In a recent development, Intel has achieved a remarkable 2x performance leap on the GPT-3 benchmark by implementing FP8 software. This achievement, validated through the industry-standard MLPerf training v3.1 benchmark, underscores Intel’s commitment to providing competitive AI solutions that can be deployed anywhere.
The Milestone Announcement
On November 8, 2023, Intel announced the groundbreaking results of its MLPerf training v3.1 benchmark for training AI models. These results encompassed Intel’s Gaudi2 accelerators and 4th Gen Intel Xeon Scalable processors equipped with Intel Advanced Matrix Extensions (Intel AMX). The standout performance came from Intel Gaudi2, which demonstrated an impressive 2x performance improvement thanks to the implementation of the FP8 data type on the v3.1 training GPT-3 benchmark. This accomplishment reaffirms Intel’s dedication to making AI accessible and efficient for a wide range of applications.
Sandra Rivera, Intel’s Executive Vice President and General Manager of the Data Center and AI Group, highlighted the significance of this achievement, stating, “We continue to innovate with our AI portfolio and raise the bar with our MLPerf performance results in consecutive MLCommons AI benchmarks. Intel Gaudi and 4th Gen Xeon processors deliver a significant price-performance benefit for customers and are ready to deploy today. Our breadth of AI hardware and software configuration offers customers comprehensive solutions and choice tailored for their AI workloads.”
By Mohamed Awad, SVP and GM, Infrastructure Line of Business
The world’s insatiable demand for compute will only continue to accelerate with the proliferation of AI. The need to process massive amounts of data gathered and transmitted by billions of devices is challenging the industry to innovate in a more specialized way. The rising cost and complexity of SoC design compounds this pressure and is driving the demand for more affordable, efficient, and performant solutions.
From AI to 5G, cloud data centers to the edge, the technology leaders building the next era of computing infrastructure are turning to custom silicon to unlock the specialized processing they need to scale.
We answered this call by introducing Arm Neoverse Compute Subsystems (CSS), a faster, lower-risk path to custom silicon for infrastructure. Neoverse CSS provides Arm technology in a new way, delivering pre-integrated and pre-verified solutions that bring more value than discrete IP to our partners. We are lowering the cost of development and accelerating time to market while allowing our partners the flexibility to focus their resources on innovation and differentiation. Partners can quickly leverage Neoverse CSS to design SoCs that are custom-built and optimized for their specific use cases.
An Intel Corporation lab in Hillsboro, Oregon, holds 24 powered-on Intel Xeon-based servers in a tank filled with synthetic non-electrically conductive oil. Immersion cooling is a method of managing heat from processors more effectively than by traditional air cooling. Intel is working with industry partners to develop solutions for today’s data centers and those in the future. (Credit: Intel Corporation)
Extending Moore’s Law means putting more transistors on an integrated circuit and, increasingly, adding more cores. Doing so improves performance but requires more energy.
Over the past decade, Intel estimates it has saved 1,000 terawatt hours of electricity through the improvements its engineers have made to processors. These advances are complemented by cooling technologies – fans, in-door coolers, direct-to-chip cooling – that further manage heat, conserve energy and reduce carbon emissions.
These cooling features require up to 40% of a data center’s energy consumption1. As Intel looks to increase performance in the future, improvements need to be accomplished in an energy-efficient way, and air cooling may not be the solution.
New Intel Xeon W-3400 and Intel Xeon W-2400 workstation processors deliver a giant leap in performance and expanded platform capabilities.
What’s New: Intel today announced the new Intel® Xeon® W-3400 and Intel® Xeon® W-2400 desktop workstation processors (code-named Sapphire Rapids), led by the Intel® Xeon® w9-3495X, Intel’s most powerful desktop workstation processor ever designed. Built for professional creators, these new Xeon processors provide massive performance for media and entertainment, engineering and data science professionals. With a breakthrough new compute architecture, faster cores and new embedded multi-die interconnect bridge (EMIB) packaging, the Xeon W-3400 and Xeon W-2400 series of processors enable unprecedented scalability for increased performance.
Researchers at Intel and QuTech, an advanced quantum computing research center consisting of the Delft University of Technology (TU Delft) and the Netherlands Organization for Applied Scientific Research (TNO), have successfully created the first silicon qubits at scale at Intel’s D1 manufacturing factory in Hillsboro, Oregon. The result is a process that can fabricate more than 10,000 arrays with several silicon-spin qubits on a single wafer with greater than 95% yield. This achievement is dramatically higher in both qubit count and yield than the typical university and laboratory processes used today.
This research was published in the journal Nature Electronics and is Intel’s first peer-reviewed research demonstrating the successful fabrication of qubits on 300mm silicon. The new process uses advanced transistor fabrication techniques including all-optical lithography to produce silicon-spin qubits, the same equipment used to produce Intel’s latest-generation complementary metal-oxide-semiconductor (CMOS) chips. The groundbreaking research is a crucial step forward in the path toward scaling quantum chips, demonstrating that it’s possible for qubits to eventually be produced alongside conventional chips in the same industrial manufacturing facilities.
Today, Intel contributed the Scalable I/O Virtualization (SIOV) specification to the Open Compute Project (OCP) with Microsoft, enabling device and platform manufacturers access to an industry standard specification for hyperscale virtualization of PCI Express and Compute Express Link devices in cloud servers. When adopted, SIOV architecture will enable data center operators to deliver more cost-effective access to high-performance accelerators and other key I/O devices for their customers, as well as relieve I/O device manufacturers of cost and programming burdens imposed under previous standards.
Today at the annual Conference on Neural Information Processing Systems (NeurIPS), two Intel-supported whitepapers on spoken language datasets are being presented. The first paper, The People’s Speech, targets “automatic speech recognition” tasks; the second is Multilingual Spoken Words Corpus (MSWC), which involves “keyword spotting.” Datasets coming out of each project contribute a sizeable volume of rich audio data, and each is among the largest collection available in its class.
The MSWC paper is co-authored by Keith Achorn, an AI frameworks engineer in Intel’s Software and Advanced Technology Group (SATG). Keith talks about his experiences on the project in a blog on the Intel Community site.
In a recent global study by Ponemon Institute,1 73% of IT decision-makers say they are more likely to purchase technologies and services from companies that proactively find, mitigate and communicate security vulnerabilities.
Intel is committed to product and security assurance and regularly releases functional and security updates for supported products and services. The Intel platform update (IPU) helps simplify the update process and improve predictability for Intel’s customers and partners. The updates provide security and functional improvements across Intel’s product portfolio.
“Security doesn’t just happen. If you are not finding vulnerabilities, then you are not looking hard enough,” said Suzy Greenberg, vice president, Intel Product Assurance and Security. “Intel takes a transparent approach to security assurance to empower customers and deliver product innovations that build defenses at the foundation, protect workloads and improve software resilience.”
In the first ‘Behind the Builders,’ Intel Fellow Johanna Swan explains how chip packaging went from a basic utility to ‘a real inflection point, maximizing performance per volume.’
Johanna Swan, Intel Fellow, Director of Package & Systemes Research, Components Research
In describing Intel’s foray into customer chipmaking through Intel Foundry Services and how it stands apart, Intel CEO Pat Gelsinger has repeatedly cited “our world-class packaging and assembly test technologies.” Gelsinger told investors last month that “we are seeing extreme interest in our packaging technologies” from potential foundry customers.
Packaging has never seen so much love.
But for Johanna Swan, deferred adoration goes with the job. As director of Package and Systems Research in Intel’s Components Research group, Swan says, “We have to anticipate what the future demands are and get focused on what we believe is going to have value — but it’s going to be five years-plus out.”
