I had the pleasure of attending the Open House for Jasper Design Automation’s new HQ in Mountain View on Thursday, September 22.   Kathryn Kranen, CEO and her staff put on a great event.  I mixed and mingled with semiconductor and EDA industry movers and shakers, tried my luck at the casino stations and enjoyed good food and drink.  There was a prize raffle at the end where Lady Luck shone on me and I won some cool items.

Kathryn graciously took some time to spend a few minutes with me and give us an update on new hiring and business at Jasper.   You can listen to the audio interview here.

Finally I took some pictures (below) at the event.  You can see we had a good time.

Enjoy!

+Graham

The 1st Nanometer Circuit Verification Forum took place on Thursday, Sept. 22 at the TechMart in Santa Clara.  Hosted by Berkeley Design Automation, the forum presented user experiences with verification of new nm high-performance analog/mixed-signal designs.   The keynote was by Jim Hogan and over 100 were in attendance.  BDA’s Analog Fast Spice product is making a big impact for design teams who need answers faster but cannot sacrifice accuracy.

I had the pleasure of speaking with Ravi Subramanian, CEO of Berkeley who gave his summary of the event in an audio interview (click here).

One of the most often heard questions at the event was “Will there be another Forum in the future”?  Because of the very positive response by the attendees to the forum’s sharing of real experiences, the answer is a resounding ‘yes’.  And there may be Forum’s held in other locations world-wide.

At the end of the forum was a reception, where I took photos.  You can see the gallery below

Enjoy!

+Graham

I received this issue of the Linley Wire and thought you would be interested in seeing the analysis of recent networking developments.

Enjoy!

+Graham

Linley Wire, Volume 11, Issue 9

September 16, 2011

Independent Analysis of the Networking-Silicon Industry

Editor: Bob Wheeler
Contributor: Jag Bolaria, Joseph Byrne, Linley Gwennap

In This Issue:

-Now Available: A Guide to High-Speed Embedded Processors
-Broadcom Acquires NetLogic
-NetLogic Previews 28nm XLP
-Cavium Enters Search Coprocessor Market
-Cortina Processor Opens Gateways
-Processor Conference October 5-6 in San Jose

To read these articles on-line, click here
http://www.linleygroup.com/newsletters/home.php?tag=1

———————————————————–

Now Available: A Guide to High-Speed Embedded Processors

The Linley Group’s new report “A Guide to High-Speed Embedded Processors” is now available for immediate delivery.  This completely revised report provides extensive coverage of high-end embedded processors with 317 pages of information on AppliedMicro, AMD, Broadcom, Cavium, Freescale, Intel, LSI, Marvell, NetLogic, STMicroelectronics, Texas Instruments, Tilera, Ubicom, Via Technologies, and Xilinx. For more details on this report, access http://www.linleygroup.com/report_detail.php?num=20

Broadcom Acquires NetLogic
By Jag Bolaria

This week, Broadcom announced that it will acquire NetLogic Microsystems for $3.7 billion. Broadcom’s largest acquisition, NetLogic will become part of the Infrastructure and Networking Group (ING) under Rajiv Ramaswami. ING rang up $1.6 billion in revenue last year, mainly on shipments of Ethernet chips, contributing about a quarter of the company’s total revenue. NetLogic adds a business that had revenue of $382 million last year and a staff of 645 employees. The NetLogic product lines that contributed the bulk of last year’s business were embedded processors and KBPs (Knowledge Based Processors). NetLogic also has a 10G Ethernet PHY product line, but this line generated significantly less revenue and was not consequential to the acquisition.

For NetLogic, consolidation at this princely sum is a wonderful exit to a charmed life. In the highly competitive search coprocessor market, NetLogic evolved from a startup to the dominant supplier while one-by-one its competitors folded operations. The company expanded its target market by acquiring RMI for $183 million, and that business grew as a result of excellent leadership and favorable market conditions. Looking forward, NetLogic faced a more challenging environment. Cavium is entering the search coprocessor market with an innovative product that has a strong potential to win market share from NetLogic. Additionally, NetLogic’s execution on its next-generation XLP processor has been weak, which had the potential to impact future growth.

As a part of Broadcom, the KBP business is more defendable, and the processor business should benefit from Broadcom’s considerable engineering and sales resources to improve execution and win market share. For Broadcom, this deal provides a family of multicore MIPS-compatible processors. The XLP processor is popular in networking and communications equipment, a market where Broadcom is currently the leading supplier of Ethernet chips. Broadcom will be able to expand its networking target market by bundling Ethernet chips with data-plane and control-plane processors. Additionally, NetLogic gives Broadcom an opportunity to become a major player in the larger embedded processor market—where the company currently has only a small share generated from legacy products.

With this acquisition, Broadcom also gets wireless base station DFE (digital front-end) chips, which came to NetLogic through its Optichron acquisition earlier this year. In the last year, ING has targeted base stations and related technologies through internal Carrier Ethernet switches and acquisitions. In 4Q10, it acquired Percello, which was developing femtocell processors. Earlier this year it acquired Provigent, which was developing microwave backhaul components. While Broadcom has built a portfolio of mobile infrastructure components, the company has yet to articulate a platform strategy that cohesively combines them all.

NetLogic Previews 28nm XLP
By Linley Gwennap

One week before the Broadcom acquisition was announced, NetLogic Microsystems announced its plans to move its XLP processor into 28nm technology, with the first products sampling in 1Q12, according to the company. The next-generation manufacturing process will enable the company to increase the number of CPUs from 8 in the current 40nm XLP to a maximum of 20 in the forthcoming XLP II family. NetLogic has set a clock-speed target of 2.5GHz for the 28nm parts, 25% faster than the target for the current XLP. With the increase in both clock speed and core count, the XLP II is rated at 100Gbps of packet-processing throughput; the company did not specify the type of processing that can be performed at this rate.

Like the XLP, the new processors will support multisocket cache-coherent implementations using proprietary chip-to-chip interfaces called ICI. The XLP II will add a fourth ICI port, enabling designs with eight processor chips and 160 CPUs working together in a single coherent memory model. This coherent model simplifies programming, eliminating the need for software pipelining or other forms of partitioning. No competing processor vendor provides scalability to this level of performance.

In most other ways, the new processors will be similar to the existing XLP, which features a four-way superscalar CPU with simultaneous multithreading and a variety of accelerators, including encryption, reg-ex, compression, de-duplication, TCP, and RAID engines. To support the additional CPUs, the XLP II will increase the size of the on-chip caches and support the latest DDR3 memory speeds. The company did not disclose details such as power dissipation or pricing for the next-generation products.

Unlike most processor vendors, NetLogic has extensive experience with 28nm technology. The company has already developed multiple products, including 10G Ethernet PHYs and search coprocessors, in TSMC’s 28nm HP technology. This experience should ease the development of the XLP II, which we assume uses the same process. Freescale has also announced plans to sample its first 28nm processor, the T4240, in 1Q12. Thus, the two companies are in a horserace to deliver the first 28nm multicore processor.

The XLP II offers impressive specifications that should keep it at the forefront of performance. By extending its unique multisocket scalability, the new processor will be particularly well suited to extremely demanding applications. A more complete analysis, however, must await a full disclosure of the product’s details.

NetLogic will disclose additional details of the XLP II architecture at the Linley Tech Processor Conference on October 5–6. For more information on this event, access http://www.linleygroup.com/events/event.php?num=10

Cavium Enters Search Coprocessor Market
By Jag Bolaria

In August, Cavium announced its upcoming family of search coprocessors. The products include the Neuron Search and the Neuronmax Search lines of coprocessors. The former is a standalone search coprocessor that integrates all required memory, while the latter uses a combination of on-chip and external memory. The primary difference between these components is the addition of a DDR3 controller in Neuronmax Search.

Scheduled to sample in 1Q12, these coprocessors perform Layer 2 through Layer 4 lookups for networking equipment in the enterprise and service provider markets. Specifically, each device can perform LPM (longest prefix match) and ACL-rule lookups. Instead of using a TCAM-based architecture, Cavium has developed proprietary technology to perform LPM and ACL lookups. The company claims Neuron Search provides 4× the capacity of a 40Mb TCAM at half the power, giving it a tremendous advantage. Neuronmax Search uses external memory to support up to 20 times the capacity of Neuron Search.

The Neuron Search family interfaces to a network processor using Interlaken LA or a parallel bus. With Interlaken, Neuron Search supports the latest NPUs, while the parallel interface supports legacy NPUs. Cavium plans to offer family members at different performance levels, ranging from 100 million searches per second to 1.6 billion searches per second with guaranteed latency.

Cavium enters the search coprocessor market at the beginning of a new growth spurt, which is driven by the move from IPv4 to IPv6 combined with greater port rates. By guaranteeing latency, Cavium has addressed the traditional issue associated with algorithmic solutions. At the same time, Neuron/Neuronmax Search are set to take the lead in capacity per watt. With its power and density advantages, Neuron/Neuronmax Search are well positioned to win designs against traditional TCAM-based search coprocessors.

Additional coverage of search coprocessors appears in our report “A Guide to Network Processors”.

Access our web site for more details: http://www.linleygroup.com/report_detail.php?num=13

Cortina Processor Opens Gateways
By Joseph Byrne

Cortina has developed a new gateway processor featuring a dual-core 400–800MHz ARM Cortex-A9. Accelerators enable 2Gbps of data-plane performance and relieve the CPUs of network-processing functions, such as network address translation (NAT), encryption, packet prioritization, upper-level MAC functions for Wi-Fi, and TCP operations including segmentation and reassembly. CPU cycles are at a premium because next-generation gateways must handle data at gigabit rates while performing services such as dishing out video to TVs and to thin-client set-top-boxes. There’s also talk of running Java applications, and even Android, on gateways. Such applications leave little time for CPUs to chase packets.

Typical of gateway processors, the CS7542 features three Gigabit Ethernet ports. In a standard configuration, one port connects to a broadband modem, another to a home-networking (e.g., Moca, HPNA, or HomePlug) chip, and the third to an Ethernet switch to fan out to other LAN ports. Three multiplexed PCI Express/SATA ports provide connections to peripherals such as Wi-Fi transceivers and disk drives. An additional unmultiplexed SATA interface brings the total of possible direct-attached drives to four, enabling construction of a four-bay home-storage (NAS) system without use of external port multipliers or controllers.

An unusual feature is the CS7542’s six MPEG Transport Stream (MPEG-TS) interfaces, which accept data from satellite, cable, and terrestrial TV receivers. The CS7542 can, for example, wrap these streams in a copy-protection layer and beam them to networked devices over its Ethernet ports. For audio output, the processor has a pair of PCM interfaces, enabling the processor to adapt VoIP to analog telephones. Ports for I2S and SPDIF provide output for high-quality audio. For displaying management information, the processor connects directly to LCD panels. High-quality video requires an external PCIe-based video decoder.

The market for PON gateways is much smaller than for DSL gateways, making it difficult for vendors of PON gateway processors to establish a profitable business. None of these suppliers has created a sustainable franchise; developing a gateway processor is clearly easier than selling one. As in DSL, broadband integration is inevitable, and Cortina is well positioned to combine its EPON controller into its gateway processor in the future. In the meantime, the CS7542 validates Cortina’s processor technology and offers some unique features that should help it win designs.

Processor Conference October 5-6 in San Jose

Twenty of the most influential suppliers of processors for networking and communications will present their newest technologies at the 2011 Linley Tech Processor Conference. Click here to see a detailed program and to register for this not to be missed event.
http://www.linleygroup.com/events/prog_day.php?num=10&day=1&num=10
Registration is free for qualified attendees.

Keynote speakers include Linley Gwennap, Principal Analyst for The Linley
Group and the industry’s premier expert on the microprocessor technology
and markets, and Christos Kolias, Network Architect at Orange and an expert
on OpenFlow and software-defined networking.

This two-day single-track event also has sessions dedicated to:

• 100Gbps networking
• Processors for base stations
• Embedded processors for data-plane processing
• Data-plane software
• Secure system design and virtualization
• Memory and memory alternatives
• Scalable and extensible processors
• Next-generation CPU designs

About Linley Wire

Linley Wire is a free electronic newsletter published by The Linley Group, a technology analysis and strategic consulting firm. Linley Wire will present our analysis of recent news on semiconductors for networking and communications. Articles are posted weekly to our web site and sent monthly via email. To access the web content directly, visit our web site.
http://www.linleygroup.com/newsletters/home.php?tag=1

Linley Wire is not affiliated with any outside vendors. We do not rent or sell our mailing list; it is used only to send you the newsletter and information on our events.

We encourage you to forward this newsletter to colleagues who may benefit from receiving this information. They may subscribe by visiting our web site.

Copyright 2011, The Linley Group

I had the pleasure of attending the GLOBALFOUNDRIES Global Technology Conference at the Santa Clara convention center on Aug. 30.   There were partnership and EDA design flow announcements from the major vendors for the new 20nm process.  By successfully taping out a test chip using flows from leading EDA vendors Cadence Design Systems, Magma Design Automation, Mentor Graphics Corporation, and Synopsys Inc., GLOBALFOUNDRIES demonstrated that it is ready for customers to begin evaluating their 20nm designs.

There was also a GLOBALSOLUTIONS ecosystem pavilion where over 40 different partners talked about their solutions.  The exhibits looked great and were easy to get around.   I took some photos of the event and you can see them below.

Enjoy!

+Graham

At SemiCon West 2011 this summer in San Francisco,  I interview a wide-range of companies from IC foundries such as  GLOBALFOUNDRIES to PCB manufacturers such as Sierra Circuits and to testing companies such as National Instruments.  And the leading EDA companies as well.

Check out all 12 interviews here.

Did you go to SemiCon West 2011?  Is the show relevant to your business?

+Graham

I was at PCI-SIG in Santa Clara this week, discovering all things PCI.    Currently PCIe 3.0 runs at 8 Gbits per second, which means lots of difficulties getting signals to arrive at their destination without experiencing losses and have eye-closures and inter-symbol interference.    There is talk about at upcoming PCIe 4.0 running at 16 Gbits per second.  Now that is FAST!

I took photos of the exhibit area and also interviewed Agileen-EEsof and SiSoft technologists about their offerings.

You can click to see the videos here:

I was at the Denali Party  by Cadence this week in San Diego during the 2011 Design Automation Conference.   I got this photo of   Ziggy Minnelli posing with a martini.  I need a caption to go with the photo.  Please use the Comments link below to submit your entry.   The winner will receive a Starbucks Gift Card and will be announced on June 21, 2011.

Good Luck!

+Graham

I am struck at how easy it is to get used to “good enough” ways of working.  Often we fail to notice new innovations that can make our tasks easier and boost our productivity and reduce risk to success.  When asked about connecting to other design team members locally and worldwide, engineers might think of a VPN link to their office computer or the headquarters email server.  However, they would be missing the exciting developments of a whole new way of working that brings collaborative resources to bear on the design process, so that design creation, verification and integration is easier and less costly to do.

Geographically diverse design teams obviously face a number of challenges in the creation and verification of the IPs that form a functioning system-on-chip (SOC).  Design teams often grow organically and have local versions of design tools, with the related licensing and operating systems to support these tools, and means to check-in and out those designs with other teams.  Design datasets require version control of their source files, and verification sign-off steps must occur at each stage of the design process.  Questions naturally arise whether design IP has been verified using the correct application and technology libraries?

Centralized location of design files is one way to improve design management, and if the CAD licenses can be run remotely as well, then this can further benefit a structured design process and eliminate the management of CAD licenses and applications locally. Some design teams have adopted remote execution of their CAD tools from a central server, but may be forced to use expensive high-bandwidth connections to support graphical intensive applications such as IC layout or suffer with low-bandwidth connections that affect display quality.

Ideally, collaboration on a design would include shared computer desktops so graphical layouts can be reviewed and updated from diverse locations. And the connectivity solution would reduce the need for expensive high-bandwidth connections.

Connectivity solutions such as Exceed onDemand from OpenText make centralized CAD environments easy to achieve.  Their high-speed thin client graphical interface to a central location is especially architected to reduce the amount of network bandwidth to display graphical content.   Even graphically intensive 3D CAD and real-time rubber banding during layout editing is now feasible for multiple team members connected to a central location.

To simplify design control and validation as it proceeds from conception to final GDSII layout, centralized hardware and software can deliver a more stable, predictable and cost-effective design process.  Verification of IC designs takes a considerable amount of compute resources and server farms stacked with multi-CPU machines are often used to attack these problems, especially as the design proceeds closer to final tape-out.

It makes good sense to centralize these resources and gives teams robust access to them.   The freedom to launch lengthy verification runs, suspend the session from an office computer and then re-connect with that session later to monitor simulation progress, or make adjustments, allows the designers to flexibility to work from multiple locations and time zones.  Disruptions in local power or network connections do not affect the success of verification runs on a robust secure central location.

Security is also an issue with design creation and collaboration.  Centralized location of design files means synchronization of local design files is minimized and encrypted communications ensure that corporate intellectual property is preserved.  Secure and managed communications with IP suppliers and third-parties means data access can controlled as needed.

Exceed onDemand from OpenText provides the capabilities needed by SOC design teams worldwide and has been adopted by leading companies in the semiconductor industry.  Cadence Design System in EDA, Renesas in semiconductor manufacturing, and Skyworks Solutions, a fabless supplier of wireless chips have all adopted and used Exceed onDemand to made design tasks easier, boost productivity and protect the security of their design IP.  Good enough can be great with the right tool to bring our world of design together.

ESC SV is taking place this week at San Jose Convention Center.   On Tuesday, before I walked the convention hall, I took the time to hear a presentation by John Bruggeman, senior vice president and CMO, Cadence and Nimish Modi, senior vice president for the System and Software Realization Group at Cadence, regarding their new  System Development Suite which features two new products.  You can read more about it here.

I had my digital audio recorder switched on during the press conference.  You can hear John Bruggeman talking about App Driven Electronics and Nimish Modi giving details for the new System Development Suite and also Kevin McDermott, ARM Dir. of Marketing presenting on Cadence Co-Verification at ARM.

Below are photos I took at the press meeting, and around the conference floor.  Enjoy!

+Graham

Design and Reuse hosted the IP SOC Day at the Hilton Hotel in Santa Clara on April 26th.  I stopped by to catch the exhibits and take some photos.   I did get to meet Gabriele Saucier, CEO and Chair of the board.  She is tireless and continues to enjoy skiing with the grand-kids besides promoting the IP community in Europe.  Her photo is the last one in the Gallery. Enjoy!