Design and Reuse hosted the IP SOC Day at the Hilton Hotel in Santa Clara on April 26th. I stopped by to catch the exhibits and take some photos. I did get to meet Gabriele Saucier, CEO and Chair of the board. She is tireless and continues to enjoy skiing with the grand-kids besides promoting the IP community in Europe. Her photo is the last one in the Gallery. Enjoy!
Archive for the ‘Uncategorized’ Category
I had the pleasure of visiting the Partner Pavillion at the TSMC Technology Symposium 2011 in San Jose on April 5. While there, I took some photos which you can see in the gallery below.
I also did an audio interview with Jim McCanny of Altos Design Automation regarding their two announcements Berkeley Design Automation and Altos Design Automation Accelerate Complex I/O Characterization and Altos New 3.1 Version Speeds IP Characterization Throughput by 2-3X. The interview can be heard here.
I also recorded an audio interview with Bernd Stamme of Kilopass regarding their announcement about the first NVM for a TSMC process: Kilopass’ TSMC 28nm HKMG Silicon Results Show Scalability of 2T Antifuse Technology. That interview can be heard here.
Enjoy the photo gallery!
Here are the Photos I took at the SNUG 2011 San Jose and Design Community Expo. Enjoy!
EDACafe again did another round of video interiws at the DVCon 2011 Conference and Exhibition in Santa Clara on Mar. 1 and 2 up in the Press Room. We didn’t use a green screen this time so we didn’t have the exhibitors’ booths in the background. If you weren’t at the show or missed some of the exhibits and announcements, then you will want to check out the videos here. I thought the interview of John Goodenough from ARM was very interesting about their use of formal verification.
Let me know what interviews you liked. And for the ones you didn’t like, what question should I have asked?
And I hope your St. Patrick’s Day was green and merry.
The Design Verification Conference and Exhibition is happening Mon. Feb. 28 through Thurs. Mar. 3 at the DoubleTree Hotel, 2050 Gateway Place in San Jose, CA.
EDACafe will be doing video interviews in the Press Room – the Silicon Valley Room at the top of the stairs – and will not be in the Exhibit Hall. There were so many new companies exhibiting we gave up our booth location so everyone could participate.
If you cannot attend the conference or just want a preview of the extensive program, then there are a number of online links you can jump to.
1. You can see the Final Conference Program here.
2. There are some additonal events that are not in the Final Program.
Strategies in Verification for Random Test Generation: New Techniques and Technologies: Tuesday, March 1
Donner Ballroom 6:30pm
Qualcomm Social Event: Monday, February 28
Donner Ballroom 6:00 – 8:00pm
3. The Technical Proceedings are now online. Below, I have expanded each of the session topics so you can jump directly to the ones that interest you.
I hope you find the event rewarding and educational.
My bad self was at the DesignCon Conference and Exhibition in Santa Clara on Feb. 1 and 2 doing video interviews in front of the green screen at the EDACafe / PCBCafe booth. If you weren’t at the show or missed some of the exhibits and announcements, then you will want to check out the videos here.
I also did a photo gallery of the exhibits. You can see the pictures here.
Let me know what interviews you like and for the ones you didn’t what question should I have asked.
Happy Presidents Day
Wednesday, January 26, 2011
By: Paul McLellan / Green Folder
Topic: Back-End — Sub-topic: New Technologies and Directions
This is an overview of the current state of 3D chips, or, in particular what has become known as 2½ D chips based on silicon interposer technology using through-silicon vias (TSVs). It is based on the keynotes at the 3D architectures for semiconductor integration
The first thing to note is the 3D chips do seem to be happening after many years of being like gallium arsenide, just a year or two more. There are designs in production, there are lots of pilot projects and the ecosystem (in particular, who does what) seems to be starting to fall into place.
The first approach to talk about is flipping one chip and attaching it to the top of another. This is done by creating bonding areas on each chip, growing (usually copper) microbumps to create die-die interconnect at a pitch of approximately 50um. The big user of this technology is in digital camera chips. The CCD image sensor is actually thinned to the point that it is transparent to light and then attached to the image processing chip. The light from the camera lens passes through the silicon to the CCD unobstructed by interconnect etc which is all on the other side of the sensor.
This approach is also used for putting a flipped memory chip onto a logic chip (see figure 1). It is not well-known, but the Apple A4 chip is built like this, with memory on top of the processor/logic chip. There are now standardization committees working on the pattern of microbumps to use for DRAMs (analagous to standard pinout for DRAMs) so that DRAM from different manufacturers should be interchangeable. Unlike in the picture, the bumps are all towards the center of the die so that the pattern is unaffected by the actual die size which may differ between manufacturers and between different generations of design.
Although this technology is formally 3D, since there are two chips, it doesn’t require any connections through any chips and is a sort of degenerate case.
The key technology for real 3D chips is the through-silicon-via (TSV). This is a via that goes from the front side of the wafer (connecting to one of the metal layers) through the wafer and out the back. The TSV is typically about 5-10um across and goes about 8-10 times its width in depth, so 50-100um. A hole is formed into the wafer, lined with an insulator and then filled with copper. Finally the wafer is thinned to expose the backside. Note that this means that the wafer itself ends up 50-100um thick. Silicon is brittle so one of the challenges is handling wafers this thin both in the fab and when they have to be shipped to an assembly house. They need to be glued to some more robust substrate (glass or silicon) and eventually separated again during assembly. The wafer is thinned using a type of CMP (chemical mechanical polishing, similar to how planarization is done between metal layers in a normal semiconductor process) until the TSVs are almost exposed. More silicon is then etched away to reveal the TSVs themselves.
Figure 2 shows Samsung’s approach. FEOL (which means front-end of line which means transistors and is nothing to do with front-end design) is done first. So the transistors are all created. Then the TSVs are formed. Then BEOL (which means back-end of line which means interconnect and is nothing to do with back-end design). After the interconnect is done then the microbumps are created. The wafer is glued to a glass carrier. The back is then ground down, a passivation layer is applied, this is etched to expose the TSVs and then micropads are created. This approach is known as TSVmiddle since the TSVs are formed between transistors and interconnect. There is also TSVfirst (build them before the transistors) and TSVlast (do them last and drill them through all the interconnect as well as the substrate).
There are two design issues with TSVs. First is the exclusion area around them. The via comes up through the active area and usually through some of the metal layers. Due to the details of manufacturing, quite a large area must be left around the TSV so that it can be manufactured without damaging the layers already deposited. The second problem is that the manufacturing process stresses the silicon substrate in a way that can alter the threshold values of transistors anywhere nearby, thus altering the performance of the chip in somewhat unpredictable ways.
There are two classes of true 3D chips which are being developed today. The first is known as 2½D where a so-called silicon interposer is created. The interposer does not contain any active transistors, only interconnect and decoupling capacitors, thus avoiding the issue of threshold shift mentioned above. The chips are attached to the interposer by flipping them so that the active chips do not require any TSVs to be created. True 3D chips have TSVs going through active chips and, in the future, have potential to be stacked several die high (first for low-power memories where the heat and power distribution issues are less critical).
The active die themselves do not have any TSVs, only the interposer. This means that the active die can be manufactured without worrying about TSV exclusion zones or threshold shifts. They need to be microbumped of course, since they are not going to be conventionally wire-bonded out.
Figure 3 shows four die bonded to a silicon interposer using microbumps. There are metal layers of interconnect on the interposer, and TSVs to get through the interposer substrate to be able to bond with flip chip bumps to the package substrate. Flip-chip bumps are similar to micobumps but are larger and more widely spaced.
In fact figure 3 is an actual production Virtex-7 FPGA from Xilinx. They call the technology “stacked silicon interconnect” and claim that it gives them twice the FPGA capacity at each process node. This is because very large FPGAs only become viable late after process introduction when a lot of yield learning has taken place. Earlier in the lifetime of the process, Xilinx have calculated, it makes more sense to create smaller die and then put several of them on a silicon interposer instead. It ends up cheaper despite the additional cost of the interposer because such a huge die would not yield economic volumes.
The Xilinx interposer consists of 4 layers of 65um metal on a silicon substrate. TSVs through the interposer allow this metal to be connected to the package substrate. Microbumps allow 4 FPGA die to be flipped and connected to the interposer. See the picture to the right. An additional advantage of the interposer is that it makes power distribution across the whole die simpler. This seems to be the only design in volume production today.
Paul McLellan is an independent consultant, blogger at EDAgraffiti.com and Managing Editor of the DAC Knowledge Center.
Prabhakaran Krishnamurthy – LSI
Senior Director, Design Tools &
Si2 Board of Directors Chair
As we turn the leaf on another successful year of collaboration at Si2, it is time to reflect on our collective accomplishments for 2010. Si2 started off the year approving the formation of a new coalition, “OpenPDK”, with the goal of improving efficiency and interoperability for the creation of process design kits (PDKs), which are used universally across our industry. We are extremely pleased with the excitement that this new coalition has created, and we now have 15 member companies who are actively contributing to support the broad technical scope of OpenPDK. This scope includes an open process specification with reference implementation and plug-ins; enhanced, standardized symbols and parameters; CDF parameter and callback standards; PDK targeting support added to the OpenDFM standard; standard Pcell parameters; OpenAccess technology file enhancements; and a standardized SPICE socket.
2010 was also a strong year of progress for Si2’s other coalitions. The OpenAccess Coalition released support for 32nm constraints and introduced multi-threading to the reference implementation. The OAC also initiated a new Extension Steering Group to approve community-based additions to the OpenAccess schema, use models, or software that do not require changes to the base standard. The DFM Coalition released the much-anticipated OpenDFM 1.0 standard to industry, complete with a reference implementation parser, plug-in generators, and suite of test cases to verify compatibility. Not only does OpenDFM standardize leading-edge DFM parameter checks, but testing by members has found it to be as much as 20x more efficient than existing DRC formats. The Low-Power Coalition published a best-practices Interoperability Guide for design teams using both CPF and UPF-1801 formats, completed work on CPF 2.0, and released a requirements document for enhanced power modeling standards. The Open Modeling TAB delivered extensions to Liberty to enable more consistent characterization and validation of macro-cell libraries.
This was also a milestone year for membership, with Si2 expanding its representation across the supply chain. As the representative of a large fabless corporation (LSI) to Si2’s Board of Directors, I am very pleased that the Board now includes a leading foundry (GLOBALFOUNDRIES) among its elected members. The OpenAccess Coalition reached a new record high of 46 member companies in 2010, with the help of semiconductor market leaders such as Samsung, and Texas Instruments. Founding membership in the OpenPDK Coalition included all major EDA vendors.
Because of an enduring value proposition to industry, Si2 has maintained financial stability even during difficult times in our global economy. Si2 managed finances well, maintaining it’s strong 2009 fund balance and achieving a 10% increase in revenues versus 2009. This provides a solid foundation to support the tremendous amount of coalition deliverables work that has been planned for 2011.
Going into 2011, Si2’s focus will be on delivering tangible return on investment value to our membership and to the industry at large, not only with newer efforts such as OpenPDK, OpenDFM, and Open3D, but also established efforts that also require ongoing innovations in OpenAccess, low power flows, and open modeling. I am proud to serve as Chairman of this fine organization, and I call for your continued support to work alongside industry leaders to improve design flow integration and interoperability for us all. Through increased membership and participation, we can remove more barriers to reduce costs and further open market opportunity.
See the entire Si2 Member Report here.
Dan Nenni, blogger, hosted the EDA Consortium CEO Annual CEO Forecast and Industry Vision Panel last night at the Double Tree Hotel in San Jose. Aart de Geus from Synopsys and Charlie Huang (filling in for Lip-Bu Tan) from Cadence and Ravi Subramanian from Berkeley talked about various trends, drivers and impacts. It was Wally Rhines from Mentor that named two possible growth numbers for 2011. One was based on a calculation what the financial analysts say for the coming year and came in at 8%.
The second figure was based on a favorite formula that says the previous year’s R&D spend is strongly correlated to the following year’s EDA growth. This formula delivered an exuberant 14%.
I like these numbers and I think we can expect hiring to pick up. As one exec over at a leading company mentioned to me, even marketing managers are finding jobs.
What do you think? Do you see 8% or 14%, and will hiring pick-up?
One more thing….the Jan. 4 issue of EDA Weekly covered The Best of 2010 – EDA Weekly Magazine, Press Postings, and Careers Corner. Check it out
Happy New Year.
I was at the Cadence CDNLive! event in San Jose on Oct. 26 at the Partner Exhibition. There were lots of vendors and you can see the Photo Gallery of the event here. I especially liked the happy staff at the Open Text booth.
I am also looking forward to the Baseball World Series moving to Texas.