India’s recent approval of three semiconductor plants, representing a colossal investment of $15.2 billion, marks a significant leap towards its ambition of becoming a global hub for electronics manufacturing and design. This initiative not only underscores India’s strategic efforts to reduce its dependency on foreign semiconductor supplies but also highlights its push to claim a stake in the highly competitive and geopolitically sensitive semiconductor industry.
The announcement comes at a time when the global semiconductor industry is facing unprecedented demand coupled with supply chain bottlenecks, exacerbated by the COVID-19 pandemic and geopolitical tensions. Semiconductors, or chips, are integral components of a vast array of products, from basic consumer electronics to advanced defense systems, making them crucial for national security and economic growth. India’s entry into semiconductor manufacturing is not just about economic development but also about securing its position in the global supply chain and enhancing its technological sovereignty.
The projects involve two fabrication plants (fabs) and one packaging facility, with Tata Group and CG Power among the key investors, in collaboration with international partners such as Taiwan’s Powerchip, Japan’s Renesas Electronics, and Thailand’s Stars Microelectronics. The construction of these plants is expected to begin within the next 100 days, highlighting the urgency and priority the Indian government places on this sector.
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New Intel Xeon W-3400 and Intel Xeon W-2400 workstation processors deliver a giant leap in performance and expanded platform capabilities.
What’s New: Intel today announced the new Intel® Xeon® W-3400 and Intel® Xeon® W-2400 desktop workstation processors (code-named Sapphire Rapids), led by the Intel® Xeon® w9-3495X, Intel’s most powerful desktop workstation processor ever designed. Built for professional creators, these new Xeon processors provide massive performance for media and entertainment, engineering and data science professionals. With a breakthrough new compute architecture, faster cores and new embedded multi-die interconnect bridge (EMIB) packaging, the Xeon W-3400 and Xeon W-2400 series of processors enable unprecedented scalability for increased performance.
In the first ‘Behind the Builders,’ Intel Fellow Johanna Swan explains how chip packaging went from a basic utility to ‘a real inflection point, maximizing performance per volume.’
Johanna Swan, Intel Fellow, Director of Package & Systemes Research, Components Research
In describing Intel’s foray into customer chipmaking through Intel Foundry Services and how it stands apart, Intel CEO Pat Gelsinger has repeatedly cited “our world-class packaging and assembly test technologies.” Gelsinger told investors last month that “we are seeing extreme interest in our packaging technologies” from potential foundry customers.
Packaging has never seen so much love.
But for Johanna Swan, deferred adoration goes with the job. As director of Package and Systems Research in Intel’s Components Research group, Swan says, “We have to anticipate what the future demands are and get focused on what we believe is going to have value — but it’s going to be five years-plus out.”
Sanjay Gangal interviewed Ben Levine, Senior Director of Product Marketing at Rambus at headquarters.
Sanjay: Tell us about your presentation at the IP-SoC Conference.
Ben: My focus area is on security, in particular hardware security cores, the idea being that you want security embedded in really any chip to provide security to the rest of the chip in the system. So my talk today was talking about that, particularly for connected devices. The fact that everything is connected to the internet these days means that every device is now exposed to a wide range of threats and attackers. So you need really strong security. So I just talked about some of the challenges, particularly around not only devices being connected, but devices being complex, what the impact is on security, and how you can solve some of those problems with our hardware security core.
Deploying vision capabilities on edge platforms requires difficult tradeoffs between latency, throughput, memory footprint, communication bandwidth, power, and cost. Luckily, there’s an ever-growing diversity of hardware choices to allow system designers to select the best option that meets their needs. Historically, hardware diversity also implied time-consuming software development to port vision applications and algorithms to a new hardware target and optimize for real-time constraints. Intel® is working with the industry to solve the puzzle of hardware diversity for traditional and deep learning-based vision at the edge.
The Intel® Distribution of OpenVINO™ toolkit(which stands for Open Visual Inference and Neural Network Optimization) enables developers to streamline the deployment of deep learning inference and high-performance computer vision applications across a wide range of vertical uses cases at the edge. The toolkit is compatible with popular open source deep learning frameworks, and enables developers to easily target execution on CPUs and accelerators (GPUs, FPGAs, VPUs, and so on) specially designed for AI inference, such as Intel® Vision Accelerator Design Products. The beauty of the toolkit is that it provides a unified and common abstraction layer for AI inference across diverse hardware targets, with a comprehensive and intuitive API that merges simplicity with optimized performance. Software simplicity and performance – just what the developer ordered!
Where do autonomous vehicles stand today and when will they be ready? How will they operate in connected cities and will consumers be ready to use them? Listen to this panel of experts working on autonomy share their perspectives on the current and future state of self-driving technology.
Qualcomm President Cristiano Amon is at CES to showcase the company’s latest inventions that are leading the world to 5G in industries from IoT to automotive.
Median income for electrotechnology and information technology professionals jumped by more than 4 percent in 2014, the largest increase in the past five years, according to the 2015 IEEE-USASalary & Benefits Survey.
Median incomes from primary sources — salary, commissions, bonuses and net self-employment income — for U.S. IEEE members working full-time in their primary area of technical competence (job specialty) rose from $124,700 in the 2013 tax year to $130,000 in 2014.
The 4.25 percent increase comes a year after median income rose by its small percentage over the past five years, .56 percent.
The results are based on survey responses from 10,215 people. Here are median incomes since 2009:
Tax Year
Median Income
% Increase
2009
$113,500
2010
$118,000
3.96
2011
$119,950
1.65
2012
$124,000
3.37
2013
$124,700
0.56
2014
$130,000
4.25
Those employed in communications technology once again enjoyed the highest median earnings ($150,000), followed by circuits and devices ($143,008) and signals and applications ($141,062).
Design engineers are increasingly spending their time on verification. Research suggests that it is now more than 50% of their time and, according to Harry Foster of Mentor Graphics in his lighter moments, if we continue the current linear trend then it will reach 100% by 2030! So why is verification so demanding? It seems that IP reuse has enabled designers to create larger, more complex designs to keep pace with our manufacturing capability but our verification productivity has not kept pace.
Looking to tools for productivity gains, EDAC (the EDA Consortium) reported that the overall EDA verification market grew by 38% from 2010 to 2012 with emulation up by 94%. But, as Mark Olen of Mentor pointed out “if Henry Ford had asked people what they wanted, they would have said faster horses”. So innovation is also required and Chris Brown of Broadcom set EDA companies the challenge of “collaborative competition” through standards. For example, UCIS has enabled TVS to build an innovative requirements sign off tool (asureSign) by reading verification data from multiple tools.
I was speaking with experts at Mentor about the latest developments in back-end physical verification (PV) and design-for-manufacturing (DFM). It prompted me to take a look at what has changed and what will be essential going forward. Here is what I see for this critical area for IC implementation.
First, we have passed the 28nm barrier and are already looking to a new generation of design. Leading-edge design starts are now at 20nm and we will see production silicon for that node by early 2013. However, in a new research brief, “Driving first-time silicon success across the IC ecosystem,” by Dr. Handel Jones, semiconductor analyst at IBS, the total number of design starts is not growing. While System integrators such as Samsung and Apple, are furiously growing their mobile businesses, the ability to integrate ever-larger collections of IP in their SOCs means they do not need to include more ICs in their phones to expand the features of their products. It is also true that 20nm designs have a much higher NRE than previous generations. Naturally, this economic incentive will keep some design starts at the 28nm and larger nodes.
