The Measure of Nanometer Silicon Success

I was speaking with experts at Mentor about the latest developments in back-end physical verification (PV) and design-for-manufacturing (DFM).  It prompted me to take a look at what has changed and what will be essential going forward. Here is what I see for this critical area for IC implementation.

First, we have passed the 28nm barrier and are already looking to a new generation of design. Leading-edge design starts are now at 20nm and we will see production silicon for that node by early 2013.  However, in a new research brief, “Driving first-time silicon success across the IC ecosystem,” by Dr. Handel Jones, semiconductor analyst at IBS, the total number of design starts is not growing.  While System integrators such as Samsung and Apple, are furiously growing their mobile businesses, the ability to integrate ever-larger collections of IP in their SOCs means they do not need to include more ICs in their phones to expand the features of their products.  It is also true that 20nm designs have a much higher NRE than previous generations.  Naturally, this economic incentive will keep some design starts at the 28nm and larger nodes.

Even so, the foundry industry is betting heavily on this next generation of silicon.  Capital investments in semiconductor equipment were in the $7B range through 2009.  Then suddenly in 2010, it jumped to $14B, and grew again to $19B in 2011.  This year the spending remains in the tens of billions of dollars.  Besides building raw capacity, foundries are spending to address the ever-growing manufacturing challenges at each smaller node.  New processes and equipment dictate new design methods and constraints, and this change affects foundry customers’ design and implementation methods and tool flows.

The motto of the U.S. Army Corps of Engineers is “The difficult we do immediately. The impossible takes a little longer.”  This also seems to be the motto of the semiconductor manufacturing industry.  If you think about it, 193nm optical lithography should be just too difficult to use at a 20nm silicon node.  Any optical image projected through a reticle mask at that node should just be a collection of fuzzy distorted shapes.  And yet they do make it work.  Various optical proximity correction (OPC) and reticle enhancement (RET) tricks have been used to modify how the shapes will be constructed using just a single mask.  Some foundries have submersed optical elements in water to improve the image resolution.  But these familiar tricks are not enough at 20nm—we need some new magic to move forward.

Double patterning is the norm at the 20-nm node.  Instead of a single mask and exposure, two different masks and two exposures are used to image critical layers. So the extra mask and processing drives NRE and manufacturing cost much higher. In addition, there are more patterns that cannot be created or are very difficult to create reliably. Future nodes at 14 or 12nm will likely use a combination of double and triple-patterning.  At some point in a single-digit nanometer era, the foundry industry will move to extreme UV but many technical challenges still remain for that technology, although everyone keeps talking about when and not if.

Mobile industry SOC designers want to use the latest generation of silicon since it provides the low power and high density they need to be competitive with their next product. But given the larger NRE costs for using advanced semiconductor nodes, they face some high-risk decisions in bringing these new designs to market and making sure they will enjoy sufficiently high yield to be profitable. Designers will have to manage this risk by building DFM tools practices into their design flows.

Traditionally, the tapeout stage of IC design uses DRC and LVS steps to ensure compliance with the foundry rules for the target process and that the layout matches the intended design.  Since the dawn of the 90nm era however, a new set of DFM issues have come to the forefront. At older nodes, the transistor structures controlled the performance of most products, but with smaller, denser circuits, the interconnect wires take on a growing importance. Feature distortions and variations in metal pitch and thickness can cause defects or significantly affect the timing of signals. Greater variability in transistor drive current, resistance or capacitance values can result in large parametric yield losses.

Mentor Graphics has invested heavily to keep up with these new challenges in its Calibre platform.  As the market leader, it has continued to expand the set of features and capabilities needed for each silicon node. For example, the Calibre platform provides pattern matching for fast identification of litho hotspots and other design rule check (DRC) violations, automatic waivers for managing rule waivers during DRC, programmable electrical rule checking (PERC) for reliability verification, and the SmartFill function to realize advanced timing-aware filling for DFM.

DP has the most direct impact on standard cell designers and custom layout engineers, since they work at the device and lowest metal layers of the layout stack. To successfully deal with all the constraints that DP places on the design, engineers need real-time, interactive support for decomposing layouts (splitting images) and guidance on how to avoid highly complex design rule errors.  Calibre provides this type of feedback directly in the design cockpit via the Calibre InRoute and Calibre RealTime products for custom and digital design respectively.

Other critical approaches to managing risk at advanced nodes include advanced reliability circuit checks and yield learning based on IC test diagnostics. Reliability checks with Calibre PERC can help eliminate subtle design flaws that are difficult to detect manually or by traditional production testing, and could result in delayed failures in the field. Yield learning through analysis of production test data using Mentor’s Tessent tools helps engineers quickly find systematic yield limiters, such as a manufacturing sensitivity to a particular design features. This enables a quicker ramp to volume production, continuous yield improvement over time, and rapid response to yield excursions that may arise in a previously stable product.

It is clear that the IC ecosystem is getting more tightly integrated to manage ever more challenging manufacturing and verification issues.  Mentor Graphics Calibre is the standard for measuring this integration and at the same time delivers this integration to all of the ecosystem partners. As the golden sign-off environment, Calibre is used by all parts of the IC ecosystem. Foundries, IP vendors, IC designers, PV teams add their knowledge and expertise to the Calibre environment to ensure a validated design flow.

Finally I want to say something about the Calibre team at Mentor Graphics.  Led by Joe Sawicki, Vice President & General Manager, Design-to-Silicon Division they have a winning attitude.  I have heard Joe say “Pessimism is for European bankers. We’re engineers, and we’re excited by the challenge.”  This combination of advanced technology and outlook makes it clear in my mind:  Calibre is the measure of nanometer silicon success.

+Graham

###

For more on Calibre as the touchstone of the IC ecosystem or to read Dr. Jones research brief “Driving first-time silicon success across the IC ecosystem”, click here.

This entry was posted on Monday, September 24th, 2012 at 1:06 pm. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.