EDACafe: The Dominion of Design

The Dominion of Design

Archive for February, 2011

DVCon 2011: Final Conference Program and Technical Proceedings Here

Friday, February 25th, 2011

The Design Verification Conference and Exhibition is happening Mon. Feb. 28 through Thurs. Mar. 3 at the DoubleTree Hotel, 2050 Gateway Place in San Jose, CA.

EDACafe will be doing video interviews in the Press Room – the Silicon Valley Room at the top of the stairs – and will not be in the Exhibit Hall. There were so many new companies exhibiting we gave up our booth location so everyone could participate.

If you cannot attend the conference or just want a preview of the extensive program, then there are a number of online links you can jump to.

1. You can see the Final Conference Program here.

2. There are some additonal events that are not in the Final Program.

Strategies in Verification for Random Test Generation: New Techniques and Technologies: Tuesday, March 1
Donner Ballroom 6:30pm

Qualcomm Social Event: Monday, February 28
Donner Ballroom 6:00 – 8:00pm

3. The Technical Proceedings are now online. Below, I have expanded each of the session topics so you can jump directly to the ones that interest you.

1 UVM In Real Life

1 Easier UVM for Functional Verification by Mainstream Users

2 OVM & UVM Techniques for Terminating Tests

3 SystemVerilog FrameWorks™ Scoreboard: An Open Source Implementation Using UVM

4 First Reports from the UVM Trenches: User-friendly, Versatile and Malleable, or Just the Emperor’s New Methodology?

1P Poster Session 1

1 A Practical Look @ SystemVerilog Coverage – Tips, Tricks, and Gotchas

2 So There’s My Bug! Debugging Universal Verification Methodology (UVM) Environments

3 Interactive Command Line Debug Using UVM Sequences

4 Consistent SystemC and VHDL Code Generation from State Charts for Virtual Prototyping and RTL Synthesis

5 Towards Provable Protocol Conformance of Serial Automotive Communication IP

2 New Frontiers In Verification

1 High-Level Synthesis Walks the Talk: Synthesizing a Complete Graphics Processing Application

2 Assertion Based Self-checking of Analog Circuits for Circuit Verification and Model Validation in SPICE and Co-simulation Environments

3 Parallel Computing for Functional Verification and Compute Farms: The Holy Matrimony

4 Mixed-Signal Approaches in Assertion Based Verification: New Frontiers

2P Poster Session 2

1 Linking Multiple Verification Flows Using Automatically Generated Assertions

2 Case Study: Power-aware IP and Mixed Signal Verification

3 Case Study: Low-Power Verification Success Depends on Positive Pessimism

4 Plugging the Gaps: SystemC and VHDL Functional Coverage Methodology

5 GoldMine: Automatic Assertion Generation and Coverage Closure in Design Validation

3 Mixed Signal Verification

1 An Innovative Methodology for Verifying Mixed-signal Components

2 Application of SystemC/SystemC-AMS in 3G Virtual Prototyping

3 Plan- & Metric-Driven Mixed-Signal Verification for Medical Devices

4 UVM-MS: Metrics Driven Verification of Mixed Signal Designs

4 UVM Enhancements

1 UVM Transaction Recording Enhancements

2 TLM2 in UVM

3 Advanced Testbench Configuration Using Resources

5 Acceleration Techniques

1 Comparison of TLM2-Quantum Keeping and TLM+-Resource Modeling with Regard to Timing in Virtual Prototypes

2 Transaction Based Acceleration – Strong Ammunition in Any Verification Arsenal

3 Off To The Races With Your Accelerated SystemVerilog Testbench

6 Pragmatic Approaches To Verification

1 A Smart Synchronizer- Pragmatic Way to Cross Asynchronous Clock Domains

2 CompMon: Ensuring Rigorous Protocol Specification and IP Compliance

3 Addressing the Verification Challenge of SERDES-based FPGAs: The Performance/Accuracy/Efficiency Trade-off

7 Low Power Verification

1 Achieving First-Time Success with a UPF-based Low Power Verification Flow

2 Low Power Static Verification- Beyond Linting and Corruption Semantics

3 Optimizing Area and Power Using Formal Methods

8 Vertical Reuse

1 Verification Patterns in the Multicore SoC Domain

2 An Experience to Finish Code Refinement Earlier at Behavioral Level

3 Stepwise Refinement and Reuse: The Key to ESL

9 UVM Applications

1 Are Macros in OVM & UVM Evil? – A Cost-Benefit Analysis

2 Parameters and OVM – Can’t They Just Get Along?

3 From the Magician’s Hat: Developing a Multi-methodology PCIe Gen2 VIP

10 Coverage Driven Verification

1 Pay Me Now or Pay Me Later

2 Functional Coverage-driven Verification with SystemC on Multiple Level of Abstraction

3 Panning for Gold in RTL Using Transactions

11 Automated Techniques

1 Traversing the Interconnect: Automating Configurable Verification Environment Development

2 Automated Approach to Register Design and Verification of Complex SOC

3 An Automatic Visual System Performance Stress Test for TLM Designs

12 Case Studies

1 Exhaustive Equivalence Checking on AMD’s Next-generation Microprocessor Core

2 Simple & Rapid Design Verification Using SystemVerilog Testbench on Intel’s Next-Generation Microprocessor

3 Getting Rid of False Errors when Verifying LSI Designs Including Non-Determinism

I hope you find the event rewarding and educational.

+Graham

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30 New DesignCon Video Interviews

Monday, February 21st, 2011

My bad self was at the DesignCon Conference and Exhibition in Santa Clara on Feb. 1 and 2 doing video interviews in front of the green screen at the EDACafe / PCBCafe booth. If you weren’t at the show or missed some of the exhibits and announcements, then you will want to check out the videos here.

I also did a photo gallery of the exhibits. You can see the pictures here.

Let me know what interviews you like and for the ones you didn’t what question should I have asked.

Happy Presidents Day

+Graham

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