Open side-bar Menu
Lauro Rizzatti - General Manager, EVE-USA
Lauro Rizzatti - General Manager, EVE-USA
Lauro is general manager of EVE-USA. He has more than 30 years of experience in EDA and ATE, where he held responsibilities in top management, product marketing, technical marketing and engineering.

Emulation Evolved, Part 2

May 7th, 2012 by Lauro Rizzatti - General Manager, EVE-USA

In my previous blog post, I began an exploration of the evolution of emulation. Indeed, over the years emulation has evolved into a mandatory component of the SoC realization process, offering multi-MHz performance, improved time-to-emulation, and simulator-like debugging capabilities—all in a compact, low-power chassis.

But emulation providers like EVE don’t have time to rest on our laurels. The challenges of SoC design and verification are continuously changing, and it’s not enough for us to simply keep pace—we need to account for future developments as well. Accounting for future evolution in emulation requires both scalability and continued innovation.

Scalability allows for additional capacity needs in the future. In the emulation space, people typically think about scalability in terms of design capacity. Designs are still keeping pace with Moore’s Law, and emulation needs to anticipate continued growth. Most emulators support extended capacity by linking multiple systems together. Long-term scalability also requires an architecture that can accept new technology, such as a chassis that can support emulation modules based on the next generation of FPGA.

Design capacity however, is only one facet of emulation. True scalability in emulation goes beyond the number of ASIC gates that can be supported, and requires a more holistic view. Emulators enable hardware/software co-verification, which requires comprehensive debugging capabilities, as well as integration into software development environments.

When it comes to hardware debugging, the waveform is still king. Much advanced technology exists to help developers find the right waveforms to look at, but many engineers still want access to the entire waveform set. Most emulators can easily produce full-chip waveforms over a limited time window, but as design sizes and test complexity increase, the streaming of full-chip waveforms over extended periods creates a bandwidth bottleneck. Parallelizing waveform generation and offloading it to server farms enables more efficient use of emulation resources and provides extended scalability in debugging.

Scalability in the emulation test environment has been one of the driving forces behind the adoption of transactors. The number of peripheral connections and configurations in SoC devices is ever-increasing, and using synthesizable peripherals rather than in-circuit components means that changing the system-level test environment is as simple as changing an instantiation. The next evolution in emulation requires that scalability to be taken further, into the EDA tool space. Emulation providers must not only continue to supply IP for the latest standards and protocols; they must also forge new alliances and provide portability and integration with the tools that are used to create the software and test environments.

Innovation is just as important as scalability, as new trends and technologies in SoC development will present new challenges for emulation. For example, as low-power strategies proliferate themselves throughout the SoC design process, the requirement for functional verification of low-power implementations is growing. Power intent formats like UPF, traditionally applied only in implementation, must now be supported in emulation for enhanced hardware debugging. At the system level, emulation providers must again move beyond just the development of the IP, contributing to the development of the underlying standard itself.

As we approach the 49th DAC, it’s a good time to not only reflect on the history of emulation, but also look toward its future. To learn more about how EVE is preparing for the next evolution of emulation, visit us at Booth #1926.

Related posts:

Leave a Reply

ClioSoft at DAC
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL

Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
TechJobsCafe - Technical Jobs and Resumes EDACafe - Electronic Design Automation GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise