News related to artificial intelligence abound this week – including a notable research work that promises to reduce training energy consumption up to one-tenth. Before proceeding to this week’s news roundup, let’s briefly mention that – as widely reported by the media – on May 15thTSMCannounced its intention to build and operate a 5-nanometer fab in Arizona. The news has spurred a lot of comments, such as the ones reported in this EETimes article.
EDA updates: Cadence, Mentor, Synopsys
Cadence has made available ten new Verification IP (VIP) solutions supporting the development of SoCs and microcontrollers for automotive, hyperscale data center and mobile applications, including CXL, HBM3, TileLink and MIPI CSI‑2sm 3.0. Also available from Cadence, a 56G long-reach SerDes IP on TSMC’s N7 and N6 process technologies. And on its part, TSMC has granted certifications for its N5 and N6 process technologies to Mentor – for a broad array of IC design tools – and to Synopsys – for digital and custom design platforms.
Investments and technology innovation are the common underlying themes of this week’s news roundup – with the recent announcement from Intel Capital, some details about the BNN approach pursued by a Japanese startup, and an overview of San Francisco Bay Area venture capital deals in first quarter 2020. Innovations – namely, social distancing wearables – are also being developed to combat the Covid-19 pandemic.
New addition to Intel Capital’s portfolio
Astera Labs, Axonne, and Xsight Labs are the three silicon startups included in the group of eleven companies now joining Intel Capital’s portfolio. Astera Labs (Santa Clara, CA) is described by Intel as “a fabless semiconductor company that develops purpose-built connectivity solutions for data-centric systems to remove performance bottlenecks in compute-intensive workloads such as artificial intelligence and machine learning.” As explained in Astera’s website, the company’s key products are “smart retimers” based on an “innovative low-latency architecture”; these devices are “designed to easily eliminate signal integrity issues for PCI-Express (PCIe) 4.0 and 5.0 interconnects in data-centric applications.” Axonne (Sunnyvale, CA) develops high-speed Ethernet network connectivity solutions for automobiles. The company website provides no further details; according to Intel, however, Axonne solutions make use of “proprietary mixed signal circuits, algorithms and digital signal processing”. Just as secretive is the website of Israel-based Xsight Labs; the Intel press release states that the company “provides new chipset designs” aimed at “accelerating next generation, cloud-based, data-intensive workloads”. The group of eleven companies joining Intel Capital’s portfolio, all described by Intel as “startups”, also includes ProPlus Electronics, a Chinese EDA company that – according to the company’s website – was founded in 2006. Tools cited in the ProPlus website include SPICE modeling, giga-scale SPICE simulations, and a “Design-for-Yield” solution.
Image credit: Intel Capital
Retaining accuracy in binary neural networks: the LeapMind approach
As recently reported by EDACafe, one of the current trends in artificial intelligence is the growing adoption of Binary Neural Networks (BNNs), where weights can only be zero or one. This approach reduces power and storage space relative to INT8 weights, still achieving a good accuracy. New BNN intellectual property is now offered by Tokio-based LeapMind with its “Efficiera” design, an ultra-low power AI inference accelerator IP targeting ASIC and FPGA circuits at the edge. Using 1 bit for weights and 2 bits for activation, the Efficiera IP implemented in a 12 nanometer TSMC process achieves a power efficiency of 27.7 TOP per Watt, a performance of 6.55 TOP per second at 800MHz, and an area of 0.442 square millimeters. LeapMind places special emphasis on new techniques aimed at retaining accuracy in binary neural networks. Some of these techniques – such as quantization-aware training and “pixel embedding” to quantize the first convolution layer – are described in this article, which includes the slides (in English) used by Hiroyuki Tokunaga, CTO of LeapMind, is his keynote speech for the recent CoolChips 23 virtual event.
Image credit: LeapMind
Beyond silicon: first quarter VC deals in the San Francisco Bay Area
As an update to our February 7th article, let’s take a quick look at Q1 2020 venture capital deals concerning tech companies based in the San Francisco Bay Area. Once again, we extracted the relevant data from the MoneyTree report published by PricewaterhouseCoopers and CB Insights – this time from the Q1 2020 edition; and once again, most of the companies cited below do not belong to the semiconductor industry. In the first quarter of this year, all five largest US investment rounds from venture capital – each above $450 million – involved Bay Area companies: JUUL Labs (electronic cigarettes, San Francisco), Joby Aviation (electric vertical takeoff and landing aircrafts, Santa Cruz), Impossible Foods (“meat from plants”, Redwood City), Lyell Immunopharma (cell-based immunotherapies, South San Francisco), and Snowflake Computing (cloud data platform, San Mateo). Accounting and finance startups saw largest M&A “exits” in first quarter 2020, and four out of five top US deals involve companies based in the Bay Area: Credit Karma (free access to personal credit scores, San Francisco), acquired by Intuit; Plaid Technologies (fintech APIs, San Francisco), acquired by Visa; Vlocity (industry-specific cloud and mobile software, San Francisco), acquired by Salesforce; and Armis (agentless device security, Palo Alto), acquired by Insight Partners. Two Bay Area companies are among the first quarter’s top five IPOs: One Medical Group (membership-based primary care practice, San Francisco) and Revolution Medicines (novel cancer drugs, Redwood City). As for emerging areas (artificial Intelligence, cybersecurity, supply chain tech, robotics, smart cities, InsurTech), top US deals in the first quarter include Pony.ai (autonomous driving technology, Fremont), Netskope (cloud security, Santa Clara), SambaNova Systems (AI system platform, Palo Alto), SentinelOne (enterprise cybersecurity, Mountain View), Sysdig (security for cloud-native DevOps workflows, San Francisco), Arctic Wolf Networks (cybersecurity services, Sunnyvale), Molekule (air purifiers, San Francisco), Cepton Technologies (lidar-based solutions, San Jose). Let’s close with the most active US venture capital firms in first quarter 2020. Four out of seven top VC firms are headquartered in Sand Hill Road (Menlo Park): Khosla Ventures, Andreessen Horowitz, New Enterprise Associates, Kleiner Perkins Caufield & Byers; and a fifth one, General Catalyst, is based in Palo Alto.
Social distancing wearables
Using smartphone-based apps to monitor social distancing obviously requires that all people carry a smartphone. When this is not possible, social distancing can be monitored by ad-hoc wearables that activate an alarm when two people get too close to one another. At least three such devices have already been developed in Europe. Kinexon (Munich, Germany) offers a wearable called SafeZone, based on a UWB (ultra wideband) sensor, that can be worn as a wristband or attached to clothing. Also based on UWB is the device developed by Belgian company Lopos, an Imec spinoff, in collaboration with Ghent university. Called SafeDistance, it enables an accurate (< 15cm error margin) distance measurement. SafeDistance will be available for sale starting 27th of May. The wearable developed by IIT (Istituto Italiano di Tecnologia, Genoa, Italy) is a wristband called iFeel-You that uses a radio signal on the Bluetooth frequencies to monitor the motion of the human body and the distance from another wristband. The device – currently a prototype, not available for sale – also sends an alert when the body temperature is higher than 37.5 degrees.
Using L-band for 5G and IoT services
The US Federal Communications Commission (FCC) has approved with conditions the application from Ligado – a company based in Reston, VA – to deploy a low-power terrestrial nationwide network in the L-Band that would primarily support 5G and Internet of Things services. Authorization has been granted after an extensive technical analysis to ensure that adjacent band operations – including the Global Positioning System (GPS), also using the L band – are protected from harmful interference. L-band is the range of frequencies from 1 to 2 gigahertz.
This week, EDACafe catches up on some of the news from the last thirty days – after four weekly articles devoted to specific topics: in particular, make sure to check out our special report on high-speed PCB design featuring interviews with Wade Smith (Ansys), Stephen Slater (Keysight), and Yuriy Shlepnev (Simberian). Let’s now move to some news, starting with an update on the upcoming Design Automation Conference: this year’s DAC will be held as a virtual event, scheduled for July 19 to 23.
Startups get zero-cost Arm IP
Early-stage silicon startups with up to $5m in funding can now take advantage of Arm’s “Flexible Access for Startups” program, granting them zero-cost access to IP from the Arm Cortex-A, -R and -M processor families, select Arm Mali GPUs, ISPs, and other foundational SoC building blocks. Startups will also be able to access Arm’s ecosystem of silicon designers, software developers, support, training and tools. Arm also announced a strategic partnership with Silicon Catalyst, an incubator focused exclusively on helping startups accelerate silicon solutions.
Arm-powered Macs?
Definitely not a startup, Apple also could be using more Arm IP in the future. The Cupertino giant is reportedly planning to start selling Mac computers with its own main processors by next year, relying on designs that helped popularize the iPhone and iPad. The future Arm-based Mac chips – which would replace the current Intel processors – will be reportedly manufactured by TSMC in a 5-nanometer process. Macs will still run the macOS operating system, rather than the iOS.
New Intel and AMD processors
And speaking of Intel, the recently announced 10th Gen Core S-series desktop processor family includes what the company claims to be “the world’s fastest gaming processor”. Dubbed Core i9-10900K, the chip can reach up to a maximum of 5.3 GHz thanks to Thermal Velocity Boost, a feature that opportunistically and automatically increases clock frequency based on how much the processor is operating below its maximum temperature. It also offers per-core hyperthreading control, allowing experienced “overclockers” to decide which threads to turn on or off on a per-core basis. Rival AMD, for its part, has announced global availability of “the world’s first x86 7nm commercial notebook processors,” the AMD Ryzen PRO 4000 Series Mobile family. The new series includes AMD Ryzen 7 PRO 4750U, that the company claims to be “the fastest business processor for ultra-thin business notebooks,” with up to 8 cores and 16 threads.
Image credit: Intel Corporation
Chinese “disruptive” flash memory chip
TechInsights, a Canadian reverse engineering firm, has recently analyzed the 64L 3D Xtacking NAND devices manufactured by Yangtze Memory Technologies Co. (YMTC), China’s first mass producer of 3D NAND flash memory chips. According to TechInsights, “There is no question that this will disrupt the 52 billion dollar NAND memory market and its respective market leaders.” Due to the Xtacking architecture in which periphery circuits and memory cell operations are processed on a separate wafer, the array efficiency and memory bit density of the YMTC device are considerably higher than conventional 3D NAND. TechInsights confirmed that YMTC’s Xtacking architecture uses two different dies for logic and memory array and employs some unique and very innovative technologies. According to TechInsights, this 64L 3D NAND flash device represents the first major competitive semiconductor product to come out of China’s state-backed investment in cutting-edge memory chips, part of the “Made in China 2025” initiative unveiled three years ago.
YMTC’s Xtacking architecture. Image credit: YMTC
More RF spectrum for Wi-Fi 6
The FCC (US Federal Communications Commission) has made 1,200 megahertz of spectrum in the 6 GHz band (5.925–7.125 GHz) available for unlicensed use. According to FCC, these new rules will usher in Wi-Fi 6, the next generation of Wi-Fi, and play a major role in the growth of the Internet of Things.
Belgian research institute Imec has presented the world’s first chip that processes radar signals using a spiking recurrent neural network (SNN). According to Imec, the neuromorphic device consumes 100 times less power than traditional implementations while featuring a tenfold reduction in latency. Its first use-case will be a low-power, anti-collision radar system for drones that can react much more effectively to approaching objects.
Imec’s neuromorphic chip. Image credit: Imec
Smartphones get advanced video technologies
A quick look at some recent announcements confirms the current role of smartphones as advanced video platforms. OmniVision has announced the OV64B, a 64-megapixel image sensor with a 0.7 micron pixel size, enabling 64 MP resolution in a 1/2″ optical format for the first time. This allows high-end and high mainstream smartphone designers to create the thinnest possible phones with high resolution 64 MP cameras. This sensor provides 4K video recordings with electronic image stabilization, as well as 8K video at 30 frames per second. MediaTek will enable YouTube video streams using the cutting-edge AV1 video codec on the MediaTek Dimensity 1000 smartphone SoC. And the fifth generation Pixelworks visual processor enables some OnePlus smartphone models to offer features such as upconversion of video dynamic range from standard (SDR) to high (HDR), automatic adaptation of the color tone of the display to match the color temperature of the ambient light, true-to-life skin tones, etc.
Acquisitions
Nvidia has recently completed its acquisition of Mellanox for a transaction value of $7 billion. The deal obviously targets datacenters and high-performance computing. Intelhas acquired Moovit, an Israel-based company offering Mobility-as-a-Service (MaaS) solutions. Upon close, Moovit will join Mobileye, the ADAS company that Intel acquired in 2017. Moovit combines information from public transit operators and authorities with live information from the user community to offer travelers a real-time picture of the best route for their journey. MaxLinear– a provider of ICs for the connected home, wired and wireless infrastructure – has entered into a definitive agreement to acquire Intel’s Home Gateway Platform Division, which comprises Wi-Fi access points, Ethernet and home gateway SoC products. New Wave Design and Verification, a provider of high-performance digital electronic interface solutions for the defense/aerospace market, has acquired FlightWire Technology, a provider of 1394b AS5643 (MIL-1394) solutions.
Artificial intelligence chips continue to be the hottest topic in the processor arena – as testified by the 2020 spring edition of the Linley Processor Conference, organized by the technology analysis firm Linley Group. Due to the Covid-19 pandemic, this year the April event – usually taking place in Santa Clara, CA – was held in a virtual format, with speakers addressing a remote audience through live streaming video. Here is a quick overview of some of the presentations.
AI trends and issues: larger models, binary weights, difficult porting
The keynote speechfromLinley Gwennap, principal analyst of the Linley Group, offered an overview of the current trends in AI architectures. The size of AI models is growing quickly to improve accuracy: as an example, in 2014 ResNet-50 had 26 million parameters, while the recent Turing NLG (Microsoft’s Natural Language Generation model) has 17 billion parameters. This obviously calls for more powerful processors, and vendors are responding with a diverse range of architectures. Most of them follow one of these two approaches: many small cores, or a few big cores. Both have advantages and disadvantages: little cores are easier to design, to replicate and scale to multiple performance/power points, while big cores require less complex interconnect and simplify compiler/software design. Recent architectural trends also include a shift from systolic arrays to convolution-optimized architectures (examples include chips from Alibaba and Kneron), and the adoption of Binary Neural Networks (BNNs), where weights can only be zero or one. This approach greatly reduces power and storage space relative to INT8 weights, still achieving a good accuracy. BNN hardware is available from Lattice and XNOR.ai (now Apple). (more…)
EDACafe Special Report: Signal Integrity and Power Integrity Challenges in High-Speed PCB Design
Part Three – Interview with Yuriy Shlepnev, President of Simberian Inc.
Signal integrity and power integrity issues are becoming increasingly challenging for designers of high-speed PCBs required by next generation applications such as 5G and new semiconductor devices such as DDR5 memories. What are the key aspects that designers should consider? What are the capabilities of the tools offered by EDA vendors to address these issues? To answer these questions, EDACafe has interviewed experts from some of the major vendors in this specific market. For part three of our special report we submitted out questions to Altium, that has partnered with Simberian – a company specializing in electromagnetic signal integrity software – to address the increasing importance of high-speed design and the need for PI and SI simulation. As a result of this partnership, Simberian’s simulation capability is integrated in the latest versions of Altium Designer. Answering our question on behalf of Altium is Yuriy Shlepnev, president of Simberian.
EDACafe: Users of Altium Designer can leverage the capabilities of Simbeor, Simberian’s electromagnetic signal integrity software. What are the benefits of this solution?
Yuriy Shlepnev: New signal and power integrity challenges should be addressed during the layout of the board. Ideally, a board designed by a layout engineer should be immediately compliant with the new signal integrity requirements and power delivery constraints. Such approach would eliminate needs for multiple tools, costly post-layout analysis and would shorten the design process. This can be achieved by embedding signal and power integrity tools into a layout tool. Use of Simbeor signal integrity solvers to compute impedance for any type of PCB interconnect in Altium Designer, is the first step in building such an integrated solution. Opportunity to control trace impedance in the beginning of the design process cannot be underestimated. Selection of materials and stackup structure are all affected by the PCB designers’ ability to achieve a target impedance, delay and losses in all critical interconnects. This can be done seamlessly in Altium Designer 20, with the user experience tailored for the layout engineers, combined with the accuracy of the extensively validated Simbeor solvers.
EDACafe Special Report: Signal Integrity and Power Integrity Challenges in High-Speed PCB Design
Part Two – Interview with Stephen Slater, Product Planning and Marketing Manager at Keysight Technologies
Signal integrity and power integrity issues are becoming increasingly challenging for designers of high-speed PCBs required by next generation applications – such as 5G – and new semiconductor devices – such as DDR5 memories. What are the key aspects that designers should consider? What are the capabilities of the tools offered by EDA vendors to address these issues? To answer these questions, EDACafe has interviewed experts from some of the major vendors in this specific market. Part two of our special report features an interview with Stephen Slater, product planning and marketing manager at Keysight Technologies. On occasion of the last DesignCon show, Keysight introduced what it claims to be “the world’s first design and test workflow solution that reduces product development time for Double-Data Rate Dynamic Random-Access Memory (DDR5 DRAM) systems.” This interview will therefore focus mainly on DDR5 and on Keysight’s PathWave solution.
Keysight’s DDR5 complete design and test solution. Reproduced with permission, courtesy of Keysight Technologies, Inc.
EDACafe Special Report: Signal Integrity and Power Integrity Challenges in High-Speed PCB Design
Part One – Interview with Wade Smith, Application Engineer Manager at Ansys
Signal integrity and power integrity issues are becoming increasingly challenging for designers of high-speed PCBs required by next generation applications – such as 5G – and new semiconductor devices – such as DDR5 memories. What are the key aspects that designers should consider? What are the capabilities of the tools offered by EDA vendors to address these issues? To answer these questions, EDACafe has interviewed experts from some of the major vendors in this specific market. Part one of our special report features an interview with Wade Smith, application engineer manager at Ansys.
EDACafe: In your view, what are the major signal integrity and power integrity challenges posed – in high-speed PCB design – by next generation applications such as 5G and by new semiconductor devices such as DDR5 memories? Can you provide practical examples of critical issues in next-generation PCB layout?
A new edge inference solutions company has been making news over the past few days, claiming an outstanding power efficiency. Other updates this week are mostly from research works in different areas.
AI edge processing at 55 TOPS/Watt
On March 31st Perceive Corporation emerged from stealth mode and debuted its first product, the Ergo edge inference processor. According to Perceive, Ergo delivers more than 4 sustained “GPU-equivalent” floating-point TOPS, with the ability to run heterogeneous, large neural networks simultaneously, and offering a power efficiency of more than 55 TOPS/Watt. For example, Ergo can run YOLOv3 at up to 246 frames per second (batch size =1) at 30 frames per second while consuming about 20 mW. The processor has a 7×7 mm package and requires no external RAM. Ergo targets applications such as video object detection, audio event detection, and speech recognition, in consumer devices such as security cameras, smart appliances, and mobile phones. Perceive also announced that Ergo has been selected by two major providers of smart connected camera and security products – one of them being Arlo – to integrate advanced neural network applications into future products. The Ergo chip and reference board are currently being sampled to leading customers; the company expects to be ready for mass production in the second quarter of 2020. Founded in 2018 and based in San Jose, CA, Perceive is a majority-owned subsidiary of Xperi Corporation, the company known for brands such as DTS, IMAX Enhanced, HD Radio, and Invensas. (more…)
There is no need to stress the impact that the current pandemic is having on every aspect and activity of the semiconductor and ICT industry. Here we will only briefly mention a couple of pandemic-related news, then move on to some of our usual market and technology updates.
Analog Devices and Infineon withdraw their market outlooks
Analog Devices “believes it is prudent to withdraw the company’s outlook for the fiscal second quarter, ending May 2, 2020,” as quantifying and forecasting the business impact of COVID-19 has become increasingly difficult. The company will provide a further update during its second quarter earnings release and call in May 2020. Infineon, for its part, is withdrawing its outlook for the whole 2020 fiscal year, citing “low visibility”. Given the uncertainty regarding the severity and the length of the pandemic`s economic impact, the German chipmaker believes that “the specific implications on sales and earnings for the 2020 fiscal year cannot be reliably assessed or quantified.”
EDA industry 2019 results
According to a report recently released by the ESD Alliance, in 2019 the EDA industry revenue reached $10.2 billion – an 8.3 percent increase over 2018. In terms of four-quarters moving average, the fastest growing EDA category was PCB & MCM with 15.1 percent, while the only slowing category was “services” with a 10.9 percent decrease. On a regional basis – again in terms of four-quarters moving average – the year 2019 saw a significant increase in EMEA and APAC (8.6 and 13.6 percent respectively), while Japan reported a 6.7 percent decrease. The Americas, EDA’s largest region, remained almost stable in 2019, with a 2.4 percent increase. Companies that were tracked by the ESD Alliance employed 45,416 professionals in Q4 2019, an increase of 6.1 percent compared to the 42,790 employed in Q4 2018.
Samsung successfully using EUV lithography for DRAM manufacturing
Samsung has announced that it has successfully shipped one million of the industry’s first 10nm-class (D1x) DDR4 DRAM modules based on extreme ultraviolet (EUV) technology. The company claims to be the first to adopt EUV in DRAM production, to overcome challenges in scaling. EUV will be fully deployed in Samsung’s future generations of DRAM, such as D1a-based DDR5 and LPDDR5 which the company expects to begin producing in volume next year. To better address the growing demand for next-generation premium DRAM, Samsung will start the operation of a second semiconductor fabrication line in Pyeongtaek, South Korea, within the second half of this year.
Samsung Electronics Hwaseong Campus (Photo: Business Wire)
Hints about El Capitan supercomputer
Last March 5th Lawrence Livermore National Laboratory, Hewlett Packard Enterprise and Advanced Micro Devices announced the selection of AMD as the node supplier for El Capitan, one of the three exascale supercomputers that the US Department of Energy plans to deploy during the next few years. The announcement provided some details, stating that El Capitan will be powered by next-generation AMD Epyc processors code-named “Genoa”, and by next-generation AMD Radeon Instinct GPUs based on a new compute-optimized architecture for HPC and AI workloads. Also on March 5th, AMD’s Financial Analyst Day offered a preview of the company’s GPU roadmap, preannouncing a “compute-optimized GPU architecture” called CDNA which will evolve into second generation CDNA 2. Now microprocessor expert Linley Gwennap has pieced together the available information to infer something more about the DOE exascale supercomputer: “[AMD] confirmed that El Capitan will feature a fourth generation Epyc processor, code-named Genoa, implemented in 5nm technology. The system will likely include the second-generation CDNA GPU. Both Genoa and CDNA 2 implement a third-generation Infinity Fabric that coherently couples the CPU with up to four GPUs. We expect CDNA 2 will use AMD’s future X3D packaging technology to combine multiple chiplets with four HBM stacks on a single substrate.” Gwennap also comments on the choice of using a single vendor for both CPU and GPU, that also applies to another DOE supercomputer which will combine Intel Xeon processors and Intel’s future Xe GPU. “This move to single-vendor CPU+GPU combinations leaves Nvidia, which dominates the world’s top supercomputers, completely out of the picture for these big American systems.”, Gwennap observes.
El Capitan. Image credit: LLNL
Extremely fast charging EV batteries
A new Li-ion battery technology promises to enable electric vehicles to run 400 kilometers (almost 250 miles) on a five-minute charge. Developing such a technology is Enevate, a company based in Irvine, CA, reportedly using an innovative anode consisting of a porous film made mainly of pure silicon. According to the company, the new inexpensive anode material will lead to a 30 percent increase in the range of electric vehicles on a single charge. Enevate’s patented process creates the porous 10- to 60-µm-thick silicon film directly on a copper foil, and includes a nanometers-thick protective coating to prevent the silicon from reacting with the electrolyte. Enevate claims that its roll-to-roll processing techniques reduce cost compared to graphite anodes and allow high-volume manufacturing. Energy density can also be increased: the company has made battery cells reaching 350 watt-hours per kilogram. Enevate is reportedly working with multiple major automotive companies to develop standard-size battery cells for electric vehicles hitting the market in 2024-2025.
Benjamin Park, Enevate’s founder and CTO. Image credit: Enevate
Small global-shutter image sensors from STMicroelectronics
Global-shutter image sensors save all pixel data in each frame simultaneously, as opposed to “rolling-shutter” operation that captures pixel data sequentially one line at a time – not the best option with moving images. Now two new global-shutter image sensors from STMicroelectronics claim high speed and very small die size. The new sensors are the VD55G0 with 640 x 600 pixels and the VD56G3 with 1.5 Mpixels (1124 x1364), measuring 2.6mm x 2.5mm and 3.6mm x 4.3mm respectively. ST claims low pixel-to-pixel crosstalk at all wavelengths, ensures high contrast for superior image clarity. Embedded optical-flow processing in the VD56G3 calculates movement vectors, without the need for host computer processing. Key to these performances is ST’s advanced pixel technology, including full Deep Trench Isolation (DTI), that enables extremely small 2.61μm x 2.61μm pixels. The ST approach allows space-saving vertical stacking of the optical sensor and associated signal-processing circuitry on the bottom die. Integrated digital circuitry incorporates hardware features including an exposure algorithm, automatic defect correction, and automatic dark calibration. These new sensors are suited to applications such as Augmented and Virtual Reality (AR/VR), Simultaneous Localization and Mapping (SLAM), and 3D scanning.
Recent announcements from Cadence and Synopsys testify that concurrent satisfaction of multiple constraints is a key challenge for today’s chip design. More news this week concern advancements in Intel’s neuromorphic initiative, a research work on IoT cross-technology wireless communication, IC market data, and an event update.
New Cadence digital full flow
The new release of the Cadence digital full flow has been enhanced to further optimize power, performance and area results. One of the enabling innovations to this goal is what Cadence has dubbed “iSpatial technology”, which integrates the Innovus Implementation System’s GigaPlace Placement Engine and the GigaOpt Optimizer into the Genus Synthesis Solution. As Cadence explained in a press release, the iSpatial technology allows a seamless transition from Genus physical synthesis to Innovus implementation using a common user interface and database. Other enhancements include the addition of machine learning capabilities, that enable users to leverage their existing designs to train the new optimization technology to minimize design margins; and lastly unified implementation, timing- and IR-signoff engines. Engine unification enhances signoff convergence by concurrently closing the design for all physical, timing and reliability targets. According to Cadence, this allows customers to reduce design margins and iterations.
The new Cadence digital full flow. Image credit: Cadence
Synopsys shifts left RTL closure
Synopsys has introduced RTL Architect, a product aiming to “shift left” (move to an earlier phase in the design flow) the RTL design closure. According to the company, RTL Architect is the industry’s first “physically aware RTL design system”, which reduces the SoC implementation cycle in half and delivers superior quality-of-results (QoR). This is obtained through a fast, multi-dimensional implementation prediction engine that enables RTL designers to predict the power, performance, area, and congestion impact of their RTL changes. The RTL Architect system is built on a unified data model that provides multi-billion gate capacity and comprehensive hierarchical design capabilities. Synopsys’ PrimePower golden signoff power analysis engine is directly integrated with the new product.
Intel’s neuromorphic system reaches 100 million neurons
Intel has recently announced the readiness of Pohoiki Springs, its latest and most powerful neuromorphic research system providing the computational capacity of 100 million neurons – the size of a small mammal brain. Pohoiki Springs, a data center rack-mounted system, integrates 768 Loihi neuromorphic research chips inside a chassis the size of five standard servers. The cloud-based system will be made available to members of the Intel Neuromorphic Research Community (INRC).
Another recent advancement concerning Loihi is a research demonstrating its ability to “smell” and recognize ten hazardous chemicals. Training was carried out using a dataset from an array of 72 sensors detecting chemicals in the air. The research, jointly carried out by Intel Labs and Cornell University, demonstrated that Loihi is particularly efficient in this task, even in the presence of significant noise and occlusion: the chip learned each “odor” with just a single sample, without disrupting its memory of previously learned scents, and showed superior recognition accuracy compared with conventional state-of-the-art methods. Key to these performances is a neural algorithm derived from the architecture and dynamics of the brain’s olfactory circuits.
Energy bursts connect different wireless standards in IoT devices
Researchers at TU Graz (Graz University of Technology, based in Graz, Austria) have developed a solution that enables direct information exchange between commercially available IoT devices that use different wireless technologies (Wi-Fi, Bluetooth, ZigBee) but the same radio frequencies. Called X-Burst, the solution is based on the wireless transmission and reception of energy pulses (energy bursts) and leverages the ability of most IoT devices to generate and detect such pulses, irrespective of the wireless standard they use. Bursts contain data packets of varying lengths, where the information is encoded in the duration of the packets. The receivers monitor the energy level in the radio channel and can thus detect the packets, determine their duration and finally extract the information they contain. According to the research team, the solution enables communication between different wireless technologies without the need for expensive and inflexible gateways. The researchers concentrated primarily on data exchange in the license-free 2.4 GHz band. The solution also enables the system clocks of the various devices to be synchronized, allowing action coordination, and negotiation of radio frequencies to minimize cross-technology interference.
U.S. IC companies maintained global market share lead in 2019
According to a report from market research firm IC Insights, 2019 regional market shares of IDMs (companies operating wafer fabs), fabless companies, and total IC sales were led by U.S. headquartered companies. U.S. companies held 55% of the total worldwide IC market in 2019 followed by the South Korean companies with a 21% share, down six percentage points from 2018. Taiwanese companies, on the strength of their fabless company IC sales, held 6% of total IC sales, one point less than the European companies. As highlighted by the report, South Korean and Japanese companies have an extremely weak presence in the fabless IC segment and the Taiwanese and Chinese companies have a noticeably low share of the IDM portion of the IC market. Overall, U.S.-headquartered companies showed the best-balanced combination of IDM, fabless, and total IC industry market share. The report also provides year-on-year (2019 versus 2018) sales growth data on a regional basis. This part of the research shows that the South Korean-headquartered companies – primarily Samsung and SK Hynix – registered a 32% sales drop, the worst of any major country/region. This was driven by a collapse in DRAM and NAND flash memory IC sales in 2019.
Linley Spring Processor Conference goes virtual
The upcoming Linley Spring Processor Conference, scheduled for early April in Santa Clara, CA, will be held as a virtual event. Attendees connected through the Internet will be able to view live-streamed presentations and interact with the speakers during Q&A and breakout sessions. The virtual conference will be online from April 6th to 9th, morning only (from 9:00 am to 1:00 pm PDT). Topics will include AI for ultra-low-power applications; 5G and AI at the network edge; datacenter processors and accelerators; AI for embedded application; processor technology.
