Cadence’s Shift-Left Approach and the Future of Advanced Package Design

At DesignCon 2025, Brad Griffin Discusses AI, Heterogeneous Integration, and the Future of Simulation

In a rapidly evolving semiconductor landscape, where artificial intelligence accelerates demand for high-performance computing, Cadence is positioning itself at the forefront of simulation and design automation. At DesignCon 2025, held at the Santa Clara Convention Center, Brad Griffin, Product Management Group Director at Cadence, discussed the company’s latest advancements in signal integrity, power integrity, thermal simulation, and electromagnetic analysis—key components in the industry’s shift toward heterogeneous integration and chiplet architectures.

“This feels like a new beginning for Cadence at DesignCon,” Griffin said. “We’ve been at this conference for over 20 years, and while printed circuit boards remain important, the industry has shifted—now, we’re packing what used to be on a board into a single package.”

That shift, fueled by Universal Chiplet Interconnect Express (UCIe) standards and high-bandwidth memory (HBM) interfaces, is dramatically increasing design complexity, data sizes, and simulation requirements. With AI chips integrating multiple chiplets on silicon interposers or organic substrates, traditional simulation flows struggle to keep up.

Tackling the Complexity of Heterogeneous Integration

As system architects move from monolithic dies to multi-die architectures, Cadence has focused on developing tools that handle the exponential growth of data in die-to-die communication. “The geometries inside advanced packages are significantly smaller than those on a printed circuit board, and that means our design databases are exploding in size,” Griffin explained.

One of the key challenges is ensuring seamless communication between chiplets. The UCIe standard, now widely adopted for die-to-die interconnects, presents signal integrity and power integrity hurdles that require advanced simulation workflows. Meanwhile, HBM interfaces, which stack memory dies for high-speed performance, generate massive amounts of data that must be validated in simulation before fabrication.

“Cadence has integrated simulation tools directly into our design platforms,” Griffin said. “If you wait until the end of the design process to simulate, you risk discovering critical issues too late. By enabling real-time, selective simulation during the design process, we’re helping engineers shift left—finding and fixing problems sooner, reducing design spins, and speeding up time to market.”

Simulation Scalability: Making AI Chip Design Feasible

One of Cadence’s major innovations is the ability to scale simulations efficiently across multiple cores, significantly reducing computation times. This is particularly crucial for AI chips, which feature multiple HBM interfaces—sometimes up to 12 in a single design—requiring enormous simulation workloads.

“In the past, engineers had to export massive 500-gigabyte designs just to perform a single simulation, often taking days,” Griffin said. “Now, Cadence’s tools extract only the necessary data, allowing simulations to run in minutes rather than days.”

Cadence’s Clarity 3D Solver plays a key role in this. Previously, full-wave 3D electromagnetic solvers were reserved for specialized problems, but as designs grow denser and more intricate, the need for signoff-quality electromagnetic analysis has become a necessity.

“We’re now seeing full-wave 3D solvers being used as a standard practice in advanced package design,” Griffin noted. “Cadence’s Clarity solver offers both accuracy and scalability, allowing companies to handle the demands of next-generation AI hardware.”

Thermal Challenges in High-Performance Systems

As AI workloads push power densities higher, thermal management has become a critical concern for engineers designing chiplet-based architectures. Without proper cooling, even the most sophisticated semiconductor designs risk overheating and failure.

“Twenty years ago, thermal analysis wasn’t something we focused on much at Cadence,” Griffin admitted. “Today, it’s the first thing our customers ask about.”

To address these challenges, Cadence developed Celsius Studio, a multi-physics simulation platform that integrates electrothermal co-simulation and computational fluid dynamics (CFD) to model heat dissipation at the chip, package, board, and system levels.

“With Celsius, electrical engineers can simulate transient thermal behavior, adjusting power consumption dynamically to prevent overheating,” Griffin said. “At the same time, mechanical engineers can model airflow, liquid cooling, and enclosure design—all in the same environment.”

Beyond conventional cooling, Cadence has also developed tools to model liquid cooling solutions, which are becoming more common in high-performance computing and data center applications. By incorporating liquid cooling models directly into the design process, engineers can optimize heat dissipation without sacrificing performance.

Fixing Broken Design Flows: From ‘Franken-Flows’ to Integrated Workflows

One of the most pressing issues facing large advanced package design is what Griffin called “Franken-flows”—disjointed design methodologies that rely on separate, uncoordinated tools for simulation, analysis, and design.

“You can’t afford to spend weeks just translating data from one tool to another,” Griffin said. “By keeping simulation inside the design environment, Cadence eliminates inefficiencies, allowing engineers to sign off on critical subsystems before finalizing the full design.”

Cadence’s shift-left approach, which integrates PCB, IC packaging, and 3D-IC design workflows with signal integrity, power integrity, thermal, and electromagnetic simulations, ensures engineers catch and correct issues early in the process.

“We’re seeing a major mindset change,” Griffin noted. “More design engineers are now directly running simulations instead of waiting for specialized signal integrity or power integrity experts to handle them. That’s accelerating development cycles and reducing design errors.”

Looking Ahead: The Future of Simulation and AI-Driven Design

As the industry moves deeper into AI-driven chip design, Cadence continues to evolve its electronic design automation (EDA) solutions. By leveraging machine learning and cloud-based simulation scalability, the company aims to further streamline heterogeneous integration workflows, making AI, high-performance computing, and next-generation semiconductor design more efficient than ever.

Cadence is also working on improving the automation of design verification, reducing the burden on engineers by enabling AI-assisted simulation and validation. These advancements will be particularly crucial as semiconductor manufacturers race to develop chips that push the limits of power efficiency and computational performance.

For engineers and designers looking to learn more, Cadence’s website offers extensive resources on Clarity, Celsius, and other simulation tools. The company is also actively collaborating with industry leaders to refine its design and verification capabilities for next-generation semiconductor technologies.

“We’re not just keeping up with the industry,” Griffin concluded. “We’re helping shape its future.”

Tags: AI chip design, Cadence, DesignCon 2025, electromagnetic analysis, heterogeneous integration, thermal simulation

Category: Cadence

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