New AI inference solutions; a new Risc-V IP player; Chips Act updates; low power EUV litho; MEMS-based air cooling

Catching up on some of the August news after the summer break, let’s start by briefly recalling Intel’s disappointing second-quarter results and the company’s cost-reduction plan: Intel will cut its headcount by more than 15%, with the majority completed by the end of 2024. Consistently with the cost-reduction plan, Intel has reportedly sold its share stake in Arm. More news this week include new solutions challenging Nvidia AI dominance, just when Nvidia’s Blackwell family is experiencing issues in reaching high volume production. According to SemiAnalysis, the problems are related to the complexity of TSMC’s CoWoS-L packaging technology and insufficient capacity for this specific version of the package.

TSMC’s European joint venture holds groundbreaking ceremony

On August 20, ESMC – a joint venture between TSMC, Bosch, Infineon and NXP – held a groundbreaking ceremony for its first semiconductor fab in Dresden, Germany. When fully operational, ESMC is expected to have a monthly production capacity of 40,000 300mm wafers on TSMC’s 28/22 nanometer planar CMOS and 16/12 nanometer FinFET process technology. Total investments are expected to exceed 10 billion euros consisting of equity injection, debt borrowing, and strong support from the European Union and German government.

Fraunhofer’s Chiplet Center of Excellence

Also based in Dresden, Germany, is the Chiplet Center of Excellence (CCoE) launched by three Fraunhofer Institutes with the purpose of partnering with industry to drive forward the introduction of chiplet technology. The CCoE will initially focus on automotive applications, developing the first workflows and methods for electronics design, demonstrator construction, and the evaluation of reliability. The Fraunhofer initiative adds to the already existing “Automotive chiplet program” from Belgian technology hub imec.

UCIe 2.0 specification

Speaking of chiplets, the UCIe Consortium has released its 2.0 Specification. The new release adds support for a standardized system architecture for manageability, and addresses the design challenges for testability, manageability, and debug (DFx) for the SIP lifecycle across multiple chiplets. Additionally, the 2.0 Specification supports 3D packaging and establishes an initial framework for interoperability and compliance testing.

AI updates: Cerebras, FuriosaAI, Recogni

Cerebras Systems, mostly known for its wafer-scale chips, has announced what it claims is “the fastest AI inference solution in the world.” According to the company, delivering 1,800 tokens per second for Llama3.1 8B and 450 tokens per second for Llama3.1 70B, Cerebras Inference is twenty times faster than Nvidia GPU-based solutions in hyperscale clouds. And, starting at just 10 cents per million tokens, Cerebras Inference is priced at a fraction of GPU solutions, providing 100x higher price-performance for AI workloads. The company also stressed that the solution maintains state of the art accuracy by staying in the 16-bit domain for the entire inference run. In a separate announcement, Cerebras has unveiled that it plans to go public.

FuriosaAI has unveiled its RNGD (pronounced Renegade) AI accelerator at the Hot Chips 2024 conference. According to the company, RNGD is positioned to be the most efficient data center accelerator for high-performance large language model and multimodal model inference. A single RNGD PCIe card delivers 2,000 to 3,000 tokens per second throughput performance (depending on context length) for models with around 10 billion parameters. RNGD uses a non-matmul (matrix multiplication), Tensor Contraction Processor (TCP) based architecture, and a compiler co-designed to be optimized for TCP that treats entire models as single-fused operations. Furiosa claims that RNGD has a total dissipated power of 150 watts, compared to more than 1000 watts for leading GPUs. With 48GB of HBM3 memory, it runs models like Llama 3.1 8B efficiently on a single card.

Recogni has launched Pareto, its logarithmic number system for Generative AI inference. According to the company, Pareto radically simplifies AI compute by “turning multiplications into additions”, which makes Recogni’s chips smaller, faster, and less energy-hungry with minimal accuracy loss. The company claims that Pareto outperforms traditional FP8 and FP16 formats, with less than 0.1% drop in accuracy with 16-bit precision and less than 1% with 8-bit precision without the need for retraining.

Credit: Recogni

Akeana, a new Risc-V IP supplier

Startup Akeana has emerged from stealth mode announcing a wide IP offering: three series of Risc-V-based processors with different performance levels, a collection of IP blocks for the creation of processor SoCs, and an AI matrix computation engine. Formed by the same team that designed Marvell’s ThunderX2 server chips, Akeana claims that its 5000 Series of extreme performance Risc-V processors outperform established competitors. The company also promises to offer “equitable licensing options, moving beyond the limitations of today’s legacy vendors and architectures.”

U.S. Chips Act funding updates: SK Hynix, TI, HP

In August, the U.S. Department of Commerce signed three non-binding preliminary memorandum of terms (PMT) to provide federal incentives under the CHIPS and Science Act. SK hynix will get up to $450 million to establish a HBM advanced packaging fabrication and R&D facility. The proposed CHIPS investment builds upon SK hynix’s investment of approximately $3.87 billion in West Lafayette, Indiana. Texas Instruments will receive up to $1.6 billion to support TI’s investment of more than $18 billion – through the end of decade – to construct three new facilities, two in Texas and one in Utah. The investment will mostly focus on current-generation and mature-node chips. HP will be granted up to $50 million to support the expansion and modernization of HP’s existing facility in Corvallis, Oregon, which spans from R&D activities to manufacturing operations. The investment will mostly focus on microfluidics and MEMS.

Lower power EUV lithography

A new architecture for EUV lithography equipment has been proposed by Professor Tsumoru Shintake of Okinawa Institute of Science and Technology (OIST), based in Okinawa, Japan. The new concept manages to use smaller EUV light sources, thus reducing costs, improving reliability and lifetime of the machines, and consuming less than one-tenth the power. The proposed architecture is shown in the image below. Left is the industry standard model currently in use. Right is the OIST model. The simplified design with just two mirrors enables the use of a light source of only 20 watts which reduces the total power consumption of the system to less than 100 kilowatts, a tenth compared to conventional technologies that often require upwards of one megawatt to run. According to OIST, the new system retains a very high contrast while also reducing mask 3D effects, achieving the required nanometer precision.

Credit: Tsumoru Shintake (OIST)
Copyright OIST (Okinawa Institute of Science and Technology Graduate University)

MEMS-based air cooling

xMEMS Labs has announced the XMC-2400 µCooling chip, the first-ever all-silicon, active micro-cooling fan for ultramobile devices and other small size products. Just over one millimeter thick, the XMC-2400 generates an air flow by moving multiple tiny MEMS flaps, as shown in this video. A single XMC-2400 chip can move up to 39 cubic centimeters of air per second with 1,000Pa of back pressure. It comes in both “side venting” and “top venting” versions, and is IP58 rated.

Acquisitions

AMD has completed its acquisition of Finland-headquartered Silo AI, the largest private AI lab in Europe, in an all-cash transaction valued at approximately $665 million. AMD has also signed a definitive agreement to acquire ZT Systems (Secaucus, NJ), a provider of AI infrastructure for hyperscale computing companies, in a cash and stock transaction valued at $4.9 billion.

Qualcomm and Sequans have entered into a definitive agreement for Qualcomm to buy Sequans’ 4G IoT technologies. France-headquartered Sequans is a designer, developer, and supplier of cellular semiconductor solutions for massive and critical IoT markets.

Xperi has entered into an asset purchase agreement with Amazon.com Services to sell substantially all the assets and certain liabilities of Perceive Corporation, a subsidiary focused on edge inference hardware and software technologies, for a gross amount of $80 million in cash.

Indian chipmaker Polymatech Electronics, specializing in sapphire-based semiconductors, has acquired Nisene Technology Group. Based in Watsonville, California, Nisene describes itself as “the world leader in automated decapsulation” equipment for the semiconductor failure analysis industry. It also provides ingots and wafers.

This entry was posted on Wednesday, August 28th, 2024 at 10:57 am. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.