Memory-based neural networks and the use of “sparse AI” at the edge are two new AI approaches included in this week’s news roundup. Reasoning failures from LLMs are discussed in our Further Reading section. But first, some EDA updates.

EDA updates: DeFacto, Ansys, Keysight, Synopsys

DeFacto and Arm have developed a joint design flow for Arm-based SoCs, covering the steps from SoC design architecture and exploration down to the generation of RTL and IP-XACT design files. The flow integrates Arm IP Explorer and Defacto SoC Compiler. The generated files are fully compatible with standard RTL2GDS SoC design flows. According to DeFacto, the joint solution significantly reduces the overall design time from specification to an SoC ready for synthesis.

Ansys is collaborating with Supermicro and Nvidia to deliver turnkey hardware, enabling acceleration for Ansys multiphysics simulation solutions. According to Ansys, sizing and configuring the right hardware for multiphysics simulation is a complex task that can significantly impact performance, cost, and productivity. Turnkey, customized hardware solutions with CPUs, GPUs, interconnects, and cooling modules allow engineers to run predictively accurate simulations more efficiently. The testing process revealed accelerations ranging from 4x to 1,600x, for different Ansys tools.

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Not surprisingly, several interesting updates this week regard artificial intelligence in one way or another. Among them, the news about robotic startup Skild attracts the attention on the marriage between AI and robotics, a promising perspective also from the point of view of the study of living beings. So far, AI has achieved incredible language-centric performance: AI can even emulate the skills of a semiconductor expert, just see the news about SemiKong below. But throughout evolution, language is just the latest addition to a range of other key functions that are still difficult if not impossible to artificially replicate. Motion control is definitely one of those key functions: still today, we have no idea of how we could build a robot performing like a playing kitten – a small mammal, very far away from human beings in the evolution tree. In nature, there is no such thing as a language skill without a body, and there has to be a reason for that. So focusing on motion control sounds like approaching the problem from the right side.

GlobalWafers to get CHIPS act funding

The U.S. Department of Commerce plans to provide up to $400 million under the CHIPS and Science Act to Taiwan-headquartered GlobalWafers to build and expand facilities in Sherman, Texas (to establish the first 300mm silicon wafer manufacturing facility for advanced chips in the United States) and in St. Peters, Missouri (to establish a new facility to produce 300mm silicon-on-insulator wafers). Further, GlobalWafers plans to convert a portion of its existing silicon epitaxy wafer manufacturing facility in Sherman, Texas to silicon carbide epitaxy wafer manufacturing, producing 150mm and 200mm SiC epitaxy wafers.

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TSMC is now Asia’s most valuable company. Reportedly, the Taiwanese foundry has reached a trillion dollar market value. Other interesting news this week include Accenture becoming a chip design powerhouse with the addition of approximately one thousand engineers to its centers in India. But first, some EDA updates.

Siemens’ new test and analysis solution

Siemens has introduced Tessent Hi-Res Chain software, a new circuit test and analysis solution for ICs at 5-nanometers and below. As IC designs progress to more advanced nodes, they become increasingly susceptible to manufacturing variations that can create defects and slow yield ramp. At these geometries, traditional failure analysis (FA) methods can require weeks or months of laboratory effort to investigate. According to Siemens, the new Tessent Hi-Res Chain tool addresses this problem by rapidly providing transistor-level isolation for scan chain defects. By correlating design information and failure data from manufacturing tests with patterns from Tessent automatic test pattern generation (ATPG), Tessent Hi-Res Chain transforms failing test cycles into actionable insights. The solution employs layout-aware and cell-aware technology to pinpoint a defect’s most probable failure mechanism, logic location, and physical location. According to Siemens, for advanced process nodes where yield ramp heavily relies on chain diagnosis, the new software can boost diagnosis resolution by more than 1.5x, reducing the need for costly extensive failure analysis cycles.

Altair’s HyperWorks 2024

Altair has unveiled the 2024 release of its HyperWorks platform for design and simulation. According to the company, the latest release delivers significant advancements in AI-powered engineering and business, mechanical and electronics systems design, and simulation-driven design and optimization.

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Google’s fifth generation Tensor G5 chip, to be installed in the next-generation smartphone Pixel 10 series, will reportedly be produced through TSMC’s 3-nanometer foundry process. If confirmed, this move will mark a shift from Google’s fourth generation Tensor G4 chip, whose productions has been entrusted to Samsung Foundry. Let’s now move to this week’s news roundup, which includes a couple of notable acquisitions.

Altair acquires Metrics, cloud-based EDA company led by Joe Costello

Metrics, a Canadian EDA company whose executive chairman is EDA veteran Joe Costello, has been acquired by Altair. Metrics has an innovative “simulation as a service” (SaaS) business model for semiconductor electronic functional simulation and design verification. According to the two companies, the Metrics digital simulator DSim, when combined with Altair’s Silicon Debug Tools, will deliver an advanced simulation environment with superior simulation and debug capabilities. The Altair-Metrics solution can run as a desktop app, on customers’ own servers, or in the cloud. Additionally, it can run very large regressions with the customer paying only for what they use. The solution supports System Verilog and VHDL RTL for digital circuits targeting ASICs and FPGAs. According to the companies, simulations can be run concurrently and at scale, removing massive amounts of time and costs from the traditional design cycle. DSim will be available through Altair One, Altair’s cloud gateway, where it will also be available for desktop download. “Customers now have a choice in design verification,” stated Altair’s CEO James R. Scapa in a press release.

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