Synopsys to reportedly buy Ansys; automotive alliances; more IEDM innovations; epitaxial graphene

As the company announced with a post on X (Twitter), “Intel Oregon welcomes major components of ASML first shipped High-NA EUV technology to help enable the continued and relentless pursuit of Moore’s Law.” Is this new piece of equipment going to help Intel advance its “5 nodes in 4 years” program? According to SemiAnalysis, double patterning with the “traditional” EUV litho equipment (low numerical aperture) is still a better option – in terms of cost and throughput – than single patterning with the new high numerical aperture litho equipment.

Credit: Intel

Let’s now move to more news, catching up on some of the updates from the last thirty days or so.

Synopsys to reportedly buy Ansys

It looks like the EDA oligopoly is bound to always be restricted to just three big companies. According to a January 5 report from The Wall Street Journal, Synopsys is in advanced talks to acquire Ansys for around $35 billion in a stock-and-cash deal. Reportedly, the two companies are now in exclusive negotiations. Rumors started with a December 22 Reuters exclusive report revealing that Synopsys had submitted an offer to acquire multiphysics simulation specialist Ansys. While the acquisition of Ansys would be a transformative event for Synopsys, there’s no doubt that the company co-founded by Aart de Geus has a long track record of acquiring other EDA players: just take a look at this list.

Arm and Cadence partner for faster SoCs for AI workloads

Cadence has joined Arm Total Design – an ecosystem program targeted at the development of customized SoCs – as an exclusive EDA partner to accelerate the development of custom SoCs based on Neoverse CSS (Compute Subsystems). As part of this collaboration, Arm and Cadence customers can accelerate their SoC design process through access to Cadence’s full-flow system-level design verification and implementation solutions. The Cadence full-flow and design IP solutions are being validated for Neoverse CSS. Additionally, mutual customers will have access to turnkey Cadence Design Services. Areas where Arm is working with Cadence include SystemReady pre-silicon verification (where SystemReady is a set of specifications that enable partners to run existing software directly on their hardware) and EDA workloads on Arm Neoverse. According to Arm, Cadence EDA tools running on Neoverse-based AWS Graviton2 instances deliver up to 40 percent TCO improvement over traditional architectures.

Europe-headquartered Risc-V joint venture now has a name: Quintauris

Announced in August, the company jointly founded by Bosch, Infineon, Nordic Semiconductor, NXP and Qualcomm has been formally established and now has a name: Quintauris. Headquartered in Munich, Germany, the company aims to advance the adoption of Risc-V globally. The initial application focus will be automotive, but with an eventual expansion to include mobile and IoT. Alexander Kocher has been appointed as Quintauris CEO.

ASRA, a Japanese initiative for chiplet-based automotive SoCs

Twelve Japan-based companies (carmakers, electrical component suppliers, semiconductor vendors, EDA vendors) have recently launched an initiative called “Advanced SoC Research for Automotive” (ASRA). The twelve companies are Honda, Mazda, Nissan, Subaru, Toyota, Denso, Panasonic Automotive Systems, Cadence Japan, Mirise (a Denso-Toyota joint venture), Renesas, Socionext, and Synopsys Japan. ASRA will focus on chiplet-based SoCs, planning for mass-production from 2030 onward.

IEDM papers: CEA-Leti, imec

Some more innovations from the IEDM conference, which was held December 9-13, 2023 in San Francisco.

French technology research institute CEA-Leti has developed a 200mm gallium nitride/silicon (GaN/Si) process technology compatible with CMOS cleanrooms that preserves the high performance of the semiconductor material and costs less than existing GaN/SiC technology. According to CEA-Leti, current GaN high-electron-mobility-transistor (HEMT) technologies used in telecom or radar applications come on small GaN/SiC substrates and require processing in dedicated cleanrooms. The high-performance SiC substrates used to grow GaN layers are very expensive and available only in relatively small size. This R&D project developed GaN/silicon technology (GaN/Si) on 200mm and later for 300mm wafer diameters in CMOS-compatible cleanrooms to reduce substrate cost and benefit from existing high-performance cleanroom facilities.

CEA-Leti also described “the world’s-first” 3D sequential integration (3DSI) of CMOS over CMOS with advanced metal line levels, which brings 3DSI with intermediate BEOL closer to commercialization. The demonstration concerned a monocrystalline CMOS stacked sequentially above an industrial CMOS platform (28nm FDSOI) and four metal levels. The top CMOS device process was carried out at 500°C in a FEOL 300mm fabrication above state-of-the art CU/ULK  28nm BEOL. According to CEA-Leti, this achievement establishes the feasibility of manufacturing high-performance silicon CMOS devices above an industrial platform, including state-of-the-art BEOL, without compromising the performance of the bottom layer. It allows reaching the full potential of 3DSI with top devices having high performance, low variability and CMOS co-integrability in contrast with BEOL transistors.

Belgian research center imec presented aluminum-nitride/gallium-nitride (AlN/GaN) metal-insulator-semiconductor high-electron mobility transistors (MISHEMTs) on 200mm Si with high output power and energy efficiency while operating at 28GHz. With these results, imec’s GaN-on-Si MISHEMT technology outperforms other GaN MISHEMT device technology in terms of performance, while the adoption of the Si substrate provides a major cost advantage for industrial manufacturing.

A working device based on epitaxial graphene

Researchers at the Georgia Institute of Technology have created “the world’s first” functional semiconductor made from graphene, using a process compatible with conventional microelectronics processing methods. The team studied epitaxial graphene on silicon carbide substrates, showing that it has a band gap of 0.6 eV and room temperature mobilities exceeding 5,000 cm2 V−1 s−1, which is 10 times larger than that of silicon and 20 times larger than that of the other two-dimensional semiconductors. According to the researchers, epitaxial graphene could cause a paradigm shift in the field of electronics.

China updates: Seida, HLMC, CXMT

Reuters has recently devoted an investigative article to Seida, a Chinese EDA startup planning to develop Optical Proximity Correction (OPC) software. Seida was reportedly founded by a former Siemens EDA executive, joined by three colleagues from the same company. The report points out that Siemens EDA is a leading OPC vendor.

China-based chipmaker Shanghai Huali Microelectronics Corp. (HLMC) has reportedly obtained a $1 billion subsidy from the so-called “Big Fund 2.” Thanks to this Chinese government funding, HLMC could reportedly become China’s second chip manufacturer (after SMIC) that’s capable of producing chips using a sub-10nm fabrication process.

According to SemiAnalysis, a paper on 3D DRAM presented at the last IEDM conference by China-based CXMT (ChangXin Memory Technologies) was a candid announcement of their blatant violation of US export controls. CXMT presented their Gate-All-Around Vertical Transistors manufactured at the 18nm half pitch. SemyAnalysis maintains that CXMT violated two different portions of the US export controls: US tools cannot be shipped to firms that fabricate 18nm half pitch DRAM devices; and US tools cannot be shipped to firms that fabricate gate all around transistors.

Acquisitions

Synopsys has acquired Imperas, a company specializing in Risc-V simulation and verification software. The acquisition has been announced with just a few words on Imperas’ LinkedIn page.

Cadence has bought Invecas, a provider of design engineering, embedded software and system-level solutions. As stated in a press release, the acquisition brings a skilled engineering team centered in Hyderabad, with expertise in custom solutions across chip design, product engineering, advanced packaging and embedded software.

GlobalLogic – a Hitachi Group company headquartered in Santa Clara, CA, providing digital engineering services – has entered into a definitive agreement to acquire Mobiveil (Milpitas, CA), a specialized embedded engineering services firm. The acquisition will expand GlobalLogic’s existing capabilities in embedded software. Mobiveil’s offering also includes silicon IP.

Germany-headquartered X-FAB Silicon Foundries has announced the planned acquisition of M-MOS Semiconductor, a Hong Kong fabless company focused on the development of MOSFET technologies. The MOSFET wafers that M-MOS sells mainly into the industrial, consumer, and automotive markets are manufactured by X-FAB.

Singapore Technologies Engineering has announced that its ST Engineering Info-Security division has entered into an agreement to acquire cryptography specialist D’Crypt from Keele Investments.

Events

CES 2024 started in Las Vegas on January 9 and will continue until January 12.

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