AI-based PCB design; SerDes and UCIe advancements; fully configurable Risc-V cores; Arm’s own silicon chip

Catching up on some of the news from the past few weeks, let’s start by noting that yet another hyperscaler is developing its own AI chip: according to press reports, Microsoft is working on a device code-named Athena, currently being tested. Microsoft is reportedly accelerating the rollout following the success of ChatGPT.

Cadence leverages AI and the cloud to speed up PCB design

The new Cadence Allegro X AI technology promises to reduce the time for PCB placement and routing tasks from days to minutes, and with equivalent or higher quality compared with manually designed boards. Reduction in design turnaround time is achieved by automating placement, metal pouring and critical net routing – leveraging a scalable architecture that uses compute infrastructure on the cloud. Placement automation using generative AI enables feasibility analysis in the early phases of design. Exploring a much larger solution space than what is possible through manual methods, the technology drives optimization of metrics such as shorter wire lengths while adhering to the design constraints. Integration with signal integrity and power integrity analysis through the Allegro X Platform enables the user to optimize the designs for electrical and thermal performance. According to Cadence, the solution achieves a 10X or more reduction in PCB design turnaround time.

New SerDes and UCIe solutions targeting TSMC’s advanced processes

On occasion of TSMC’s 2023 North America Technology Symposium, multiple partners of the Taiwanese foundry announced new SerDes IPs and silicon, important elements to enable the realization of chiplet-based devices. Alphawave Semi revealed its first connectivity silicon platform on TSMC’s most advanced 3-nanometer process, its ZeusCORE Extra-Long-Reach (XLR) 1-112Gbps NRZ/PAM4 SerDes IP. Cadence unveiled its 112G Extended Long-Reach (112G-ELR) SerDes IP on TSMC’s N4P process. Marvell demonstrated multiple silicon interconnects produced on TSMC 3-nanometer process, including 112G XSR SerDes, Long Reach SerDes, PCIe Gen 6 / CXL 3.0 SerDes, and a 240 Tbps parallel die-to-die interconnect.

Closely related to SerDes announcements are some recent updates concerning design solutions for multi-die devices and the tape-out of UCIe IP. Synopsys collaborates with TSMC and Ansys for multi-die system design and manufacturing. A key element of the combined solution is Synopsys 3DIC Compiler, a multi-die co-design and analysis platform that integrates with TSMC’s 3Dblox standard and TSMC 3DFabric technologies. Power and thermal signoff for multi-die systems is addressed through Synopsys signoff solutions, integrated with Ansys RedHawk-SC Electrothermal multi-physics technology. Synopsys achievements in the multi-die area include the successful tape-out of the company’s UCIe PHY IP on the TSMC’s N3E process. Cadence, too, has announced the tape-out of its 16G UCIe 2.5D advanced package IP on TSMC’s N3E process, implemented on TSMC’s 3DFabric CoWoS-S silicon interposer technology.

Risc-V updates: Renesas, Esperanto, Semidynamics

Renesas has introduced a Risc-V MCU designed for voice-controlled HMI (human-machine interface) systems. Esperanto Technologies has ported and is running a range of generative AI models on its low power Risc-V hardware. Several versions of Meta’s Open Pre-Trained Transformer (OPT) model are now running on Esperanto’s hardware at multiple precision levels and context sizes, with power levels as low as 25W per chip for inferencing. Spain-based Semidynamics has emerged from stealth mode announcing what it claims is the world’s first fully customizable 64-bit Risc-V family of cores. The new core IPs enable the customer to have total control over the configuration, including new instructions, separate address spaces, new memory accessing capabilities, etc. Features include a technology specifically designed for recommendation systems, and the capability of moving a cache line per clock up to 2.4 GHz. The cores are process agnostic with versions already being supplied down to 5-nanometer.

GlobalFoundries sues IBM

GlobalFoundries has sued IBM for trade secret misappropriation. The complaint refers to technologies collaboratively developed by the two companies, over decades, at the Albany NanoTech Complex – technology that IBM has recently shared with Intel and Japan’s Rapidus. In 2015 IBM sold its microelectronics business to GF, therefore – the latter company maintains – the rights concerning those technologies exclusively belong to GlobalFoundries. The complaint notes that IBM’s executives have described the Intel and Rapidus partnerships as based on decades of technology derived from research conducted at the Albany NanoTech Complex.

Arm to collaborate with Intel Foundry and to reportedly develop its own silicon prototype

Intel Foundry Services (IFS) and Arm have announced a “multigeneration” agreement to enable chip designers to build low-power SoCs on the Intel 18A process. The collaboration will focus on mobile SoC designs first, but allows for expansion into other application areas. According to Intel, the agreement will offer fabless companies more foundry options when is comes to manufacturing SoCs that include Arm cores. IFS and Arm will undertake design technology co-optimization (DTCO) to improve power, performance, area and cost for Arm cores targeting Intel 18A process technology. Intel 18A features the PowerVia technology for power delivery and RibbonFET gate-all-around transistor architecture. IFS and Arm will jointly develop a mobile reference design.

In a separate news, the Financial Times reported that Arm is developing a silicon prototype to demonstrate the capabilities of its designs, seeking to fuel growth following its IPO later this year. To develop these prototype chips, the company has reportedly created a new “solutions engineering” team led by Kevork Kechichian, who – among other things – has previously overseen the development of Qualcomm’s Snapdragon chip. As reported by the Financial Times, the Arm’s chipmaking move has sparked fears that the company might change its business model, ceasing to be a neutral IP licensor and becoming a fabless chip vendor. According to sources quoted by the newspaper, however, this is not the case. What can be inferred from the report is that – despite its undisputed leadership in mobile phones and other areas – Arm feels the need to demonstrate that its designs can outperform competitors such as Apple’s own chips. To this goal, instead of relying on its licensees, Arm might prefer taking control of the implementation, probably through design technology co-optimization (DTCO).

Acquisitions

Germany-headquartered Bosch plans to acquire assets of the U.S. chipmaker TSI Semiconductors, based in Roseville, California. Over the next years, Bosch intends to invest more than 1.5 billion USD to convert the TSI facilities to 200-millimeter silicon carbide wafers, targeting electric vehicle applications. As stated in a press release, “The full scope of the planned investment will be heavily dependent on federal funding opportunities available via the CHIPS and Science Act as well as economic development opportunities within the State of California.”

This entry was posted on Friday, April 28th, 2023 at 6:25 am. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.