Intel to acquire Tower; AMD-Xilinx deal completed; Foxconn-Vedanta to make chips in India

Foundries and fabs are making news again this week, along with the completion of one of the mega-deals announced in 2020 (AMD-Xilinx). As for the one that did not go through (Nvidia-Arm), a recent press report suggest that an Arm IPO will probably mean SoftBank accepting a valuation below the $32 billion it paid for the company in 2016 – and well below the $60 billion expected from the transaction.

Intel to acquire specialty foundry Tower Semiconductor

Confirming rumors, on February 15 Intel announced it will acquire Israel-headquartered foundry Tower Semiconductor for approximately $5.4 billion. With this transaction, Intel aims to create a globally diverse end-to-end foundry offering, bringing together its advanced nodes and scale manufacturing with Tower Semiconductor’s specialty technologies. Tower specializes in the manufacturing of analog semiconductor solutions addressing multiple markets, including aerospace and defense. Its process platforms include SiGe, BiCMOS, mixed-signal/CMOS, RF CMOS, CMOS image sensor, non-imaging sensors, integrated power management (BCD and 700V), and MEMS. The company also provides design enablement and process transfer services. Tower Semiconductor owns two manufacturing facilities in Israel (150mm and 200mm), two in the U.S. (200mm), three facilities in Japan (two 200mm and one 300mm) which it owns through its 51% holdings in TPSCo and is sharing a 300mm manufacturing facility being established in Italy with STMicroelectronics.

Tower Semiconductor headquarter in Israel. Credit: Tower Semiconductor

AMD completes acquisition of Xilinx

Xilinx is now officially an AMD company: the acquisition, in an all-stock transaction, was completed on February 14. Former Xilinx CEO Victor Peng will join AMD as president of the newly formed ‘Adaptive and Embedded Computing Group’ (AECG). Presenting the deal to investors, AMD obviously stresses the benefits of combining the two company’s assets, in terms of IP, TAM, R&D, and technologies – including 2.5D/3D die stacking and packaging solutions, chiplet and interconnect technology etc. As for research and development, combined resources climb to $3.8 billion, with over 15,000 engineer headcount. In terms of software solutions, the investor presentation stresses AMD’s ROCm – an open-source software development platform for HPC/Hyperscale-class GPU computing – and Xilinx’s Vitis unified platform. As a result of the merger, it seems reasonable to expect some future addition to AMD/Xilinx software along the lines of Intel’s oneAPI.

Foxconn and Vedanta to jointly establish a fab in India

Taiwanese electronic manufacturer Foxconn and Indian industrial group Vedanta have signed a memorandum-of-understanding to form a joint venture company that will manufacture semiconductors in India. According to the MOU, Vedanta will hold the majority of the equity in the JV, while Foxconn will be the minority shareholder. Vedanta Chairman Anil Agarwal will be the Chairman of the joint venture company. The collaboration between Vedanta and Foxconn follows the Indian Government’s recent policy announcement for Electronics Manufacturing & PLI scheme for incentivizing organizations to contribute towards development of this sector. Discussions are currently ongoing with a few Indian State Governments to finalize the location of the plant. Vedanta Group is a global diversified group of companies with presence in metals, mining, oil & gas, power, telecom and glass. It also has a presence in electronics and technology business through group companies Avanstrate – a manufacturer of LCD glass substrates with sites in Japan, Taiwan and Korea – and Sterlite Technologies (STL), a Mumbai-based integrator of digital networks also providing 5G RAN solutions. The MOU with Vedanta follows another recent Foxconn move, last August’s acquisition of Macronix’s 6-inch wafer fab and equipment in Hsinchu Science Park, specializing in manufacture and development of wide bandgap semiconductors, especially SiC.

Upcoming virtual events

DVCon U.S. (Design & Verification Conference & Exhibition) will take place as a virtual conference from February 28 to March 3.

DATE Conference (Design, Automation and Test in Europe) is scheduled as a virtual event from March 14 to 23.

Tackling verification challenges

Part of the program of the upcoming DVCon, a tutorial from Siemens EDA (David Aerne, Vijay Chobisa, Kurt Takara and Harry Foster) will address several interesting issues concerning verification, as preannounced by this long abstract. Quoting a survey from Wilson Research Group, the authors state that over two thirds of ASIC and FPGA projects are still completed behind schedule. This prompts some fundamental questions about the strategy being pursued by the industry to tackle the verification challenges. A key problem is that verification complexity grows at a substantially greater rate than design complexity. The Wilson Research Study shows that, since 2007, the mean peak number of design engineers working on a project has increased by 32% while the mean peak number of verification engineers has increased 143%. According to the Siemens EDA authors, this is unsustainable. Tutors will then try to answer a key question: “Instead of trying to verify the bugs out, what if we could avoid putting them in in the first place?” Bug avoidance approaches proposed by Siemens EDA include linting, automatic formal applications, and other static analysis techniques. Another part of the proposed approach is based on the assumption that “regardless of the programming language used, the number of bugs is directly proportional to the number of lines of code being written.” Therefore, “by designing and verifying at a higher level of abstraction using fewer lines of code, we can minimize the number of bugs introduced.” In other words, Siemens EDA advocates “a design and verification flow using C++ and high-level synthesis,” followed by an automated RTL generation process and verification re-use methodology that delivers RTL that is correct-by-construction. Last element of this approach, a unified hardware-assisted verification system, spanning from hybrid virtual platforms to emulation and FPGA-based prototyping.

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