Open side-bar Menu
 EDACafe Editorial

Archive for October, 2021

TSMC and Samsung Foundry roadmaps; new Alibaba processors; Arm Virtual Hardware for IoT

Monday, October 25th, 2021

Chips built using 2-nanometer processes will enter volume production in 2025; this, at least, is what we can expect based on the roadmap updates recently provided by both Samsung Foundry and TSMC. For the 2-nanometer node, the South Korean company will adopt its version of the gate-all-around transistor architecture; TSMC is also considering GAA, but has not committed to it yet. More news this week include a 60-billion transistor chip from Alibaba, and a multi-pronged Arm initiative meant to boost the IoT market. But first, a couple of EDA updates.

Ansys adds a charging/discharging simulation solution

Ansys has added EMA3D Charge to its simulation solution portfolio. Developed by Colorado-based Electro Magnetic Applications company, EMA3D Charge enhances predictive accuracy for charging and discharging events that can have an impact on safety for a wide range of electric/electronics products. Leveraging Ansys SpaceClaim, the solution combines CAD import, design and simplification, simulation setup and meshing, and result generalization and visualization into one solver technology. According to Ansys, EMA3D Charge fills a need in a marketplace in which no other simulation product exists, providing a unified end-to-end workflow.

Cadence to speed up ISO 26262 and IEC 61508 certification

Cadence has announced the Cadence Safety Solution, a new offering featuring integrated analog and digital safety flows and engines for faster ISO 26262 and IEC 61508 certification. Targeting safety-critical applications – such as automotive and aerospace – the solution includes a new failure modes, effects, and diagnostic analysis (FMEDA) offering called the Cadence Midas Safety Platform, allowing to perform FMEDA-driven analog and digital verification of safety-critical semiconductors.


Discovering Cadence Integrity 3D-IC platform

Monday, October 18th, 2021

Cadence’s Vinay Patwardhan explains how designers can tackle the challenges posed by 3D ICs using the new solution recently announced by the company

Placing multiple chips in a single package – either in a 2.5D or in a 3D fashion – is emerging as a viable solution to continue advancing IC performance and functionalities using the currently available process nodes, while keeping die size within lithography reticle limits. However, a package containing two or more dies can be considered as a new type of system, posing new system-level challenges. Existing EDA tools – even the most advanced ones – are mostly meant to address the challenges posed by a single chip and its package; for this reason, the EDA industry is now coming up with new solutions specifically addressing the needs of 2.5D and 3D ICs. Cadence, in particular, has recently announced a new platform called “Integrity 3D-IC”, which it describes as the “industry’s first comprehensive 3D-IC platform for multi-chiplet design and advanced packaging”. To know more about this solution, EDACAfe’s Sanjay Gangal has conducted a video interview with Vinay Patwardhan, Product Management and Group Director, Digital and Signoff Group at Cadence Design Systems.


GloFo to go public; Intel’s Risc-V-based soft processor; Chinese investments in Q3; pixel-shift for smartphones

Wednesday, October 13th, 2021

Geopolitical tensions made headlines over the past few days, with Chinese President Xi Jinping in his recent speech reportedly vowing to pursue reunification with Taiwan. Needless to say, this news is also relevant to the semiconductor industry as Taiwan is homeland of the world’s largest foundry. Let’s now move to this week’s updates, which include a quick look at some companies based in mainland China attracting significant investments.

GlobalFoundries to go public

GlobalFoundries has publicly filed a registration statement with the U.S. Securities and Exchange Commission (the SEC) relating to the proposed initial public offering of its ordinary shares. GF has applied to list on the Nasdaq Global Select Market under the ticker symbol GFS.

Intel offers a Risc-V-based soft processor for its FPGAs

The new generation of Nios, the soft processor for Intel FPGAs, is based on the open-source Risc-V Instruction Set Architecture. Called Nios V, the family currently includes a micro controller – Nios V/m – based on Risc-V: RV32IA, with atomic extensions, 5-stage pipeline, and AXI4 interfaces. Future releases will include a general-purpose processor, an application-class processor, and a Linux-capable processor. Benefits cited by Intel include the open-source ecosystem – toolchains, debuggers, real-time operating system – and performance improvements over the Nios II/e processor. The new Nios V soft processor is available in the Intel Quartus Prime Pro Edition Software starting with version 21.3.


New MathWorks release; Arteris IP to go public; compact Risc-V IP; Arm-based servers for AI workloads; new Loihi chip

Wednesday, October 6th, 2021

Catching up on some of the news from the last couple of weeks or so, let’s briefly recall that European Union politicians have started discussing about a plan to support the semiconductor industry in the Old Continent. The President of the European Commission, Ursula von der Leyen, has recently preannounced a European Chips Act. “We need to link together our world-class research, design and testing capacities,” she said in her recent State of the Union speech. “We need to coordinate EU and national investment along the value chain. The aim is to jointly create a state-of-the-art European chip ecosystem, including production. That ensures our security of supply and will develop new markets for ground-breaking European tech. (…) We are world leaders. So let’s be bold again, this time with semi-conductors.” Additional details on the upcoming European Chips Act have been provided by European Commissioner Thierry Breton in this blog post, quoting Imec, CEA-Leti and Fraunhofer as key European assets. “I believe that we should explore setting up a dedicated European Semiconductor Fund,” he wrote. “With the European Chips Act, our tech sovereignty is within reach.”

Copyright European Union, 2021. Photographer: Christophe Licoppe

EDA/IP updates: Cadence, MathWorks, Arteris IP, Bluespec, Sigasi

The new Cadence Helium Virtual and Hybrid Studio is a platform that accelerates the creation of virtual and hybrid prototypes of complex systems. According to Cadence, Helium Studio makes verification with a virtual or hybrid model of the SoC orders of magnitude faster than verification with a pure RTL model, and it also enables early software bring-up before the RTL is available. Natively integrated with the Cadence verification engines – including Palladium Z2, Protium X2 and Xcelium – the new Helium Studio accelerates system development by verifying embedded software/firmware on pure virtual and hybrid configurations even when the RTL is not ready.


Verific: SystemVerilog & VHDL Parsers
True Circuits DDR PHY

© 2022 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
TechJobsCafe - Technical Jobs and Resumes EDACafe - Electronic Design Automation GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise