Scaling challenges and the increasing importance of design-technology co-optimization

Not just lithography: scaling to 2-nanometers and beyond involves many difficult manufacturing challenges. A virtual event and a series of blog posts from Applied Materials help understand how these problems can be solved with coordinated solutions based on new transistor architectures, new materials, new manufacturing processes

Over the past few years, the transition to EUV lithography has received a lot of attention as a key enabling technology for further IC scaling. But moving to the next advanced process nodes is not just about projecting smaller patterns; in fact, the resulting size reduction of every circuit feature opens a set of new, complex problems that need to be addressed in order to achieve the expected PPA benefits. Let’s take a look at these challenges with the help of Applied Material’s experts. In a ‘Logic Master Class’ held as a virtual event last June 16^th – still available on demand – and in a series of related blog posts, Mike Chudzik, Mehul Naik and Regina Freed addressed different aspects of the scaling of logic ICs, stressing the increasing importance of ‘design-technology co-optimization’ (DTCO). Applied Materials describes DTCO as a way to “reduce area-cost without changing the lithography and pitch,” using a combination of architectures, processes and materials. In this quick overview of the class, we will only summarize some of the general concepts.

Pitch scaling is not enough

The need for innovation stems from the fact that just building a smaller version of the same device – as in the traditional method, called pitch scaling or ‘intrinsic scaling’ – would lead to bad power and performance results and to increased device variability. This is because size reduction generates new limiting factors. Trying to generalize, one could say that there are mechanical limitations, electrical limitations, and process limitations. Mechanical limitations include the fact that some elements may become too weak to withstand mechanical stress; electrical limitations mostly refer to the increased resistance of current paths – signal or power – due to smaller cross section area; and process limitations include the fact that certain specific elements – e.g. certain material layers – cannot scale proportionally, or that patterning inaccuracy become a larger percentage of the intended feature. Collectively, these limitations are now determining the transition from FinFET to GAA (Gate-All-Around) transistors.

Limitations to further FinFET scaling

Further FinFET scaling would incur mechanical, electrical and process limitations. As explained by Mike Chudzik, at every new generation the fins that form the gate of the transistor have become taller and narrower – to increase speed – making them more fragile and susceptible to bending during the manufacturing process. This degrades performance and power efficiency while increasing transistor variability. In another part of the transistor, the interface and high-k layers haven’t scaled at the same rate as other physical parameters, which is a problem as the scaling of these layers is critical to boost transistor drive current. Lastly, in the transistor source/drain zone, scaling has reduced transistor contact area, which in turn has driven up resistance. Another process-related limitation is that – as fins are thinner and thinner – controlling fin width has become harder with each new process shrink, which has led to increased variability in threshold voltages.

Gate-All-Around: benefits of horizontal ‘fins’

As explained by Mike Chudzik, a key benefit of the Gate-All-Around architecture is that the elements functionally equivalent to fins are placed horizontally, instead of vertically. This solves the problems of fin bending and fin width variability. In finFETs, fin width is determined by lithography and etch – the process steps needed to create a fin by removing material on both sides – while in GAA, due to the horizontal position of the ‘fin’, the dimension that needs to be controlled is thickness. This allows to do without litho-etch, replacing them with epitaxy that ensures high thickness precision.

Credit: Applied Materials

Interconnects: towards the ‘buried power rail’ architecture

Let’s now move to interconnects (metal lines and metal vias), briefly summarizing Mehul Naik’s blog post and class lesson. In interconnections, the size reduction brought about by scaling causes higher resistance due to smaller cross section area, which means lower speed (higher RC delay) and power waste. A process limitation contributes to higher resistance, too: in the line-via contact, the interface (composed by a tantalum nitride barrier and a cobalt liner) does not scale proportionally with the rest of the features, so it takes up a larger percentage of the available space and reduces room for conductive copper. A way to solve both problems is doing without the TaN/Co interface, which is also the largest contributor to the via’s overall resistance. But this requires a whole new process, as the one recently announced by Applied Materials. Looking forward, scaling will require a dramatic architecture innovation: moving the power distribution network to the back side of the wafer, with ‘buried power rail’. This will achieve three benefits: smaller standard cell area, as the power rail is a major contributor to cell size; lower resistance for the power distribution network, as supplying power from the back side enables shorter paths; wider signal lines, thanks to less routing congestion on the top side – resulting in lower resistance.

Credit: Applied Materials

Reducing patterning defects

Pitch scaling can also bring about patterning defects such as opens and shorts, since line edge roughness approaches 30% of line width. As explained by Regina Freed, patterning defects can be reduced by co-optimizing deposition and etch processes with integrated metrology. Other DTCO examples include the “Single Diffusion Break”, where dual insulating structures between adjacent transistors are replaced by a single, higher quality structure to save space.

A range of classes

Applied Material’s ‘Logic Master Class’, a one-hour event, obviously includes a lot more content – about the technological challenges, the solutions being proposed by the company, the market scenario. A previous class was devoted to memory devices, and two more classes have been scheduled for ‘ICAPS & advanced packaging’ – where ICAPS stands for IoT, Comms, Auto, Power, Sensor – on September 8 and ‘Process control and AI^x platform’ on October 18.

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