New fabs; Intel reorganization; ML in FPGA design; thermal model standard; reducing via resistance

According to industry association SEMI, semiconductor manufacturers around the world will start the construction of nineteen new high-volume fabs by the end of this year, and ten more fabs will be added in 2022. So it’s no surprise that several announcements this week concern new fabs. Besides rumors about a new European site, Intel is in the news also for its organizational changes that – to some extent – reflect the growing importance of AI and hyperscale data centers. Among other news is a further advancement of machine learning in EDA-related technologies, namely FPGA design tools; and a new manufacturing process enabling further scaling.

Intel reportedly in talks on a new fab near Munich, Germany

Intel is reportedly in talks with the German state of Bavaria to build a new fab, with the goal of countering the chip shortage that is damaging the automotive industry. According to the report, in recent months Intel has been seeking 8 billion euros (US$9.5 billion) in public subsidies to build a semiconductor manufacturing site in Europe. Reportedly, the Bavarian Economy Minister is strongly supporting the initiative. The Bavarian government has suggested a disused air base in Penzing-Landsberg, west of Munich, as a possible location for the factory. The German state of Bavaria is home to carmaker BMW, and the Munich area is a significant semiconductor manufacturing hub, hosting – among others – a large Texas Instruments factory.

Globalfoundries to build a new fab in Singapore

Globalfoundries has announced the construction of a new fab on its Singapore campus. In partnership with the Singapore Economic Development Board, the plant will be funded with co-investments from committed customers and more than US $4B from GF. The company has planned capacity expansions also at all its manufacturing sites in the U.S. and Germany. When complete, the new Singapore fab will add capacity for 450,000 wafers per year, bringing the campus up to approximately 1.5 million (300mm) wafers per year.

A new Bosch fab in Dresden, Germany

German technology giant Bosch has recently opened a new fab in Dresden, Germany, which will be used to produce ASICs and power semiconductors – mostly for automotive applications. The plant works on 300-millimeter wafers and is equipped for process nodes up to 65 nanometers. The 1 billion euros funding was provided by the German federal government.

The new Bosch fab in Dresden, Germany. Credit: Bosch

Organizational changes and new appointments at Intel

Intel’s new CEO Pat Gelsinger continues to reorganize the company. Recent news includes the addition of new executive officers, and changes to the business units. Intel’s former Data Platform Group (DPG) will be restructured into two new business units: ‘Datacenter and AI’ focused on data center products, including Xeon and FPGAs, led by Sandra Rivera; and ‘Network and Edge Group’, led by Nick McKeown who joined Intel with its 2019 acquisition of Barefoot Networks, which he co-founded. Intel will also create two new business units: ‘Software and Advanced Technology Group’, led by Greg Lavender who has just joined Intel; and ‘Accelerated Computing Systems and Graphics Group’, led by Raja Koduri. Greg Lavender – a former colleague of Pat Gelsinger at VMware – will also serve as Intel chief technology officer (CTO) and, as such, will also be responsible for Intel Labs. The four people’s executive leadership team – Rivera, McKeown, Lavender and Koduri – will report directly to Pat Gelsinger. Navin Shenoy, who has been serving as executive vice president and general manager of the Data Platforms Group, will leave Intel.

Pat Gelsinger. Credit: Intel

IPU aka DPU

Intel has also recently discussed its vision for what it calls “infrastructure processing unit” (IPU); other vendors, such as Nvidia or Fungible, call this category of devices “data processing unit” (DPU). In Intel’s view, the IPU has dedicated functionality to accelerate modern applications that are built using a microservice-based architecture in the data center. Intel quoted research from Google and Facebook showing that 22% to 80% of CPU cycles in data centers can be consumed by microservices communication overhead. As of today, Intel’s IPU are implemented on FPGAs, but the company’s first ASIC IPU is under test.

Xilinx adds machine learning to Vivado design suite

The new Vivado ML Editions enables machine learning-based algorithms that accelerate design closure. The technology features ML-based logic optimization, delay estimation and intelligent design runs, which automates strategies to reduce timing closure iterations. Besides saving development time, Xilinx claims quality of results (QoR) improvements on average 10% for complex designs, compared to the current Vivado HLx Editions. The new Vivado release is also introducing the concept of an Abstract Shell, which allows users to define multiple modules within the system to be compiled incrementally and in parallel. According to Xilinx, this enables an average compile time reduction of 5x and up to 17x, compared to traditional full system compilation. Abstract Shell also helps protect a customer’s IP by hiding the design details outside of the modules.

New standard for thermal model data sharing

Siemens has announced the establishment of JEP181—a neutral file, XML-based standard from JEDEC – that simplifies thermal model data sharing between suppliers and end-users in a single file format called ECXML (Electronics Cooling eXtensible Markup Language). According to Siemens, thermal model data availability and sharing is one of the key limiting factors of thermal simulation throughout the product design process. The new standard – proposed and chaired by Siemens – promises to enable importing commercial 3D simulation tools from software suppliers. The JEP181 standard is targeted at high power density applications such as miniaturization, 2.5D and 3D semiconductor packaging, and 5G technology.

Applied Materials reduces via resistance for 3nm processes

On occasion of its recently held 2021 Logic Master Class, Applied Materials described a method – already being used by leading foundries – to reduce via resistance for the 3-nanometer process node and beyond. The method is meant to offset the via resistance increase brought about by scaling, due to the smaller section area of metal interconnection. Higher resistance translates into power waste: according to the company, wiring already consumes a third of the power in smartphone chips. The new solution, called Endura Copper Barrier Seed IMS (Integrated Materials Solution), combines seven different process technologies in one system under high vacuum: ALD, PVD, CVD, copper reflow, surface treatment, interface engineering and metrology. The combination replaces conformal ALD with selective ALD, eliminating a high-resistivity barrier at the via interface. The solution also includes copper reflow technology that enables void free gap fill in narrow features. Electrical resistance at the via contact interface is reduced by up to 50 percent. An animation of the process sequence can be viewed at this link: https://bit.ly/3g8HMe1.

Endura Copper Barrier Seed IMS. Credit: Applied Materials

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