Higher density DRAM alternative; faster simulations; new chip prototyping program

Chip shortage and foundry activity continue to make headlines. Tesla is reportedly considering paying in advance for chips to secure its supply, and is said to be even exploring the acquisition of a semiconductor fab. GlobalFoundries is reportedly working with Morgan Stanley on an initial public offering that could value the foundry at about $30 billion. Let’s now move to some process technology and EDA updates.

Vertical nanowire-based memory promises 4X DRAM density without special materials

Singapore-based Unisantis unveiled the developments of its Dynamic Flash Memory (DFM) technology at the recent IEEE International Memory Workshop. According to the company, DFM offers faster speeds and higher density when compared to DRAM or other types of volatile memory. DFM is also a type of volatile memory, but since it does not rely on capacitors it has fewer leak paths, and it has no connection between switching transistors and a capacitor. The result is a cell design with the potential for significant increases in transistor density. Additionally – as it offers ‘block erase’ like a Flash memory – DFM reduces the frequency and the overhead of the refresh cycle and can deliver significant improvements in speed and power compared to DRAM. Based on TCAD simulation, Unisantis claims that DFM can potentially achieve a 4X density increase compared to DRAM. So, while the scaling of DRAM has almost stopped at 16Gb, DFM could be used to build 64Gb memory devices. Unisantis points out that unlike the so-called ‘emerging memory technologies’ (MRAM, ReRAM, FRAM, PCM), its Dynamic Flash Memory does not require using additional materials on top of a standard CMOS process. DFM was developed by Unisantis with the principles of its patented surround gate transistor (SGT) technology, also referred to in the semiconductor industry as a vertical nanowire transistor. According to the company, the benefits of this technology include improved area density, compared to planar and FinFET transistors; reduced leakage power, due to the strong electrostatic control of the surrounding gate to the transistor channel; and the possibility of optimizing the transistor width and length for different power/performance combinations. Unisantis is working on SGT technology in collaboration with Belgian research institute Imec.

DFM structure. Credit: Unisantis

Faster circuit simulator

Cadence has announced its new Spectre FX Simulator, a FastSPICE circuit simulator targeted at the verification of memory and large-scale SoC designs. According to Cadence, the Spectre FX Simulator offers up to 3X better performance compared to the latest FastSPICE simulators with equal or better accuracy. The tool enables to include post-layout parasitics in the chip verification process, an important feature especially for advanced-node designs. Other benefits claimed by Cadence include scalability of up to 32 cores with multi-threading to parallelize transient simulations; an intuitive use model requiring a minimal amount of tuning to obtain the optimal accuracy and simulation speed; easy adoption into existing Spectre and SPICE flows; extensive verification capabilities, including static and dynamic circuit checking, alters, sweeps and Monte Carlo analyses.

Accessing cloud resources for 3D electromagnetic simulations

Another new product recently introduced by Cadence is Clarity 3D Solver Cloud, a new approach to gaining access to compute resources in the cloud when executing 3D electromagnetic simulations. Clarity 3D Solver Cloud provides the ability to scale 3D finite element method simulation capacity from 32 cores to thousands of cores using secure connections to Amazon Web Services (AWS). This hybrid approach gives users the option to simulate using local compute resources or cloud simulation resources without having to add to either on-premises or cloud computing budgets. Cloud simulations keep design data safe on local computers while sending only encrypted simulation-specific data to the cloud. Clarity 3D Solver Cloud automatically sets up and simulates in a private and secure AWS chamber, accessing the user-defined number of compute cores. Simulation results are returned to the local on-premises computer(s) while the data in the secure AWS chamber is immediately deleted.

Broadening access to chip fabrication

Efabless, a community chip creation platform, has launched its new “chipIgnite” program and a collaboration with U.S. foundry SkyWater Technology for the first node supported in the program. The chipIgnite program expands upon the SKY130-based open source chip manufacturing program sponsored by Google and supports private commercial designs that include non-open source IP. In Efabless’ intentions, this initiative represents another step forward in the industry to broaden access to chip design by giving people the ability to more easily create and fabricate chips. SkyWater’s open source 130 nm CMOS platform will be used to fabricate chips for the chipIgnite program. The program provides users 10 square millimeters of total silicon area, for projects using the SkyWater Open Source PDK. According to Efabless, the program is a good fit for users who want to create an initial prototype or proof-of-concept for an IP block or full SoC. The starting price of $9750 per project includes 100 QFN or 300 WCSP packaged parts and five evaluation boards. The first manufacturing run in the chipIgnite program is optimized for university digital and mixed-signal chip design courses, with a submission deadline for tapeout of June 18, 2021. The delivery of parts and assembled boards is planned for early October. The first shuttle in the chipIgnite program will support fabrication of student projects as part of the EE272B course in the Electrical Engineering department at Stanford University for senior undergraduate and graduate students.

Upcoming virtual events

Computex Taipei 2021 will take place from May 31 to June 30, with keynotes from Simon Segars, CEO of Arm; Lisa Su, President and CEO of AMD; Sanjay Mehrotra, President and CEO of Micron; Charles Liang, Founder, President and CEO of Supermicro; and Kurt Sievers, President and CEO of NXP Semiconductors.

CadenceLIVE Americas 2021 is scheduled for June 8-9.

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