Running as a virtual event from Saturday through Friday, December 12-18, this years’ edition of IEDM (IEEE International Electron Devices Meeting) will offer a mix of live-streamed video content (such as the plenary presentations, panel discussion and career session) and on-demand pre-recorded presentations, with a schedule of live Q&A sessions. The event’s program includes more than 220 papers, plus tutorials and short courses. Part of the papers will cover emerging topics through six focus sessions: cryogenic electronics; GaN and SiC; future interconnect; technologies enabling 5G and beyond; energy harvesting and wireless power transmission; DTCO of advanced logic and memory. As a quick preview of the event, let’s now have a look at some of the technical highlights from the presentations.

Intel’s future transistor: stacked NMOS-on-PMOS nanoribbons

Next generation FET architectures for logic devices are a much-debated issue in the industry, and at IEDM Intel researchers will present a new candidate: a NMOS-on-PMOS transistor built from multiple self-aligned stacked nanoribbons. This architecture employs a vertically stacked dual source/drain epitaxial process and a dual metal gate fabrication process, enabling different conductive types of nanoribbons to be built so that threshold voltage adjustments can be made for both top and bottom nanoribbons. According to Intel, this approach combines excellent electrostatics (subthreshold slope of <75 mV/dec) and DIBL (Drain Induced Barrier Lowering, <30mV/V for gates ≥30nm) with a path to significant cell size reduction due to the self-aligned stacking. These devices were used to build a functional CMOS inverter with well-balanced voltage transfer characteristics.

The evolution of transistor architectures from planar, to FinFETs, to nanoribbons and to a 3D CMOS architecture. Credit: Intel