PLM; Ru interconnect; CNT pellicles; Intel-Sandia collaboration; 10Mbps Ethernet on a twisted pair

Catching up on some of the news from the last thirty days or so, this week’s focus is on both EDA-related innovations and on new process materials/equipment. Completing our updates, some application-specific news and several acquisition announcements.

SoC Lifecycle Management

Product lifecycle management (PLM) – a long established concept in the avionics and automotive industries – is becoming increasingly important for the development of SoCs. Two recent announcements highlight different aspects of PLM solutions targeted at SoCs: IP management and post-silicon analysis, respectively. Methodics IPLM 3.0 is the new version of the IP lifecycle management platform developed by Methodics, a company that was acquired by Perforce earlier this year. Aimed at managing the planning process of SoCs, the new platform allows what-if analysis of early design prototypes (build vs. buy vs. reuse of IP), and automates the delivery of an IP bill of materials (BoM) to development teams.

Methodics IPLM also adds new security solutions addressing the concerns related to sharing IP and global IP leakage. Synopsys, for its part, has recently unveiled its Silicon Lifecycle Management (SLM) platform, described as “the industry’s first data-analytics-driven approach to optimizing SoCs from the design phase through to end-user deployment.” The Synopsys SLM platform is based on two principles: 1) gather as much useful data about each chip as possible, by adding information obtained through monitors and sensors that are embedded in the chip; 2) analyze that data throughout the chip’s entire lifecycle using analytics engines to enable optimizations at each stage of the semiconductor lifecycle, up to in-field operation.

Synopsys Silicon Lifecycle Management Platform. Credit: Synopsys

System-level verification IP

Cadence has announced System-Level Verification IP (System VIP), a new suite of tools and libraries for automating SoC testbench assembly, bus and CPU traffic generation, cache-coherency validation and system performance bottleneck analysis. According to Cadence, System VIP can improve chip-level verification efficiency by up to 10X.

Ruthenium a promising alternative to copper and cobalt for metal interconnect

Belgian research institute Imec has demonstrated electrically functional 2-metal-level interconnects fabricated with ruthenium semi-damascene and airgap technology, showing a long lifetime and good mechanical strength. A complementary 12-metal-layer analysis confirmed the system-level benefits of this semi-damascene technology in terms of RC, power consumption and IR drop. The research also showed ruthenium as a promising alternative for contact plugs in the ‘middle-of-line’ of advanced process nodes. As explained by Imec, alternative metallization materials such as ruthenium, and alternative metallization approaches such as semi-damascene, are intensively researched to scale the back-end-of-line (BEOL) and middle-of-line (MOL) towards the 2nm technology node and beyond.

Imec research on ruthenium. Semi-damascene enables high-aspect-ratio wires (a-c) and high-density airgap (d). Credit: Imec

Carbon nanotube pellicles a viable solution for EUV photomask protection

Imec has also demonstrated the successful fabrication and scanner handling of full-field carbon nanotube-based pellicles as a protection for photomasks used in EUV lithography. Tests conducted by the Belgian institute on an ASML NXE:3300 EUV scanner showed that the CNT pellicles had a single-pass EUV transmission up to 97%. The impact on imaging was found to be low and correctable. As Imec underlines, developing EUV pellicles is very challenging, since the 13.5nm wavelength is absorbed by most materials. In addition, stringent thermal, chemical, and mechanical requirements must be achieved. According to Imec, the new CNT pellicle has the potential to withstand EUV scanner powers beyond 600 Watts.

A carbon nanutube pellicle developed by Imec. Credit: Imec

Intel and Sandia collaborate on neuromorphic computing

Intel Federal LLC – the wholly owned subsidiary on Intel formed in 2011 to work with the U.S. government – has announced a three-year agreement with Sandia National Laboratories to explore the value of neuromorphic computing for scaled-up computational problems. Sandia will start its research using a 50-million neuron system based on Loihi – Intel’s neuromorphic chip – that was delivered to its facility in Albuquerque, New Mexico. This work with Loihi will lay the foundation for the later phase of the collaboration, which is expected to include research on Intel’s upcoming next-generation neuromorphic architecture and the delivery of Intel’s largest neuromorphic research system to date, which could exceed 1 billion neurons.

Breaking the one-mile barrier for 10-Mbps Ethernet signals on a twisted pair

Texas Instruments has introduced a new Ethernet physical layer capable of transmitting 10-Mbps full-duplex Ethernet signals up to 1.7 kilometers through a single pair of twisted wires. Called DP83TD510E, the new PHY is mainly targeted at factory and building automation applications, where it will allow the replacement of fragmented systems based on multiple fieldbus protocols – which require protocol conversion through network gateways. The new PHY will also enable reusing existing two-wire fieldbus infrastructure – such as 4- to 20-mA current loops – for Ethernet-based data and power transmission.

 Accelerating AI-based video compression R&D

InterDigital, a US-based mobile and video technology R&D company, has developed CompressAI, an open source software platform to simplify and accelerate AI-based video compression research. CompressAI allows researchers to quickly design, train, test, and evaluate AI-based codecs. The platform includes five software modules: data loader, data formatting, reference layers, pretrained models, benchmarking.

Acquisitions

Network-on-chip IP supplier Arteris IP will acquire the assets of French EDA company Magillem, which offers a chip design and assembly environment. Substantially all Magillem team members will be joining Arteris IP. Magillem’s software products will continue to be offered separately from the Arteris interconnect IP offerings.

Israel-based Foretellix, a company developing solutions to enable measurable safety for advanced automatic driving systems, has announced that it will acquire Metamoto (Redwood City, CA), which offers a cloud-based “simulation as a service” solution for testing and validating automotive software. Following the acquisition, Foretellix will open a US R&D center to expand its US operation. The combined Metamoto and Foretellix team will comprise approximately 60 employees in the US, Europe and Israel.

Microchip has announced the acquisition of Tekron, a New Zealand-based provider of high-precision GPS and atomic clock time-keeping technologies and solutions for the smart grid and other industrial applications. These products will complement the existing Microchip synchronization and timing offering, which is focused on communications, enterprise, government, military and aerospace applications.

STMicroelectronics has announced the acquisition and integration of the assets of Somos, a French fabless semiconductor company specialized in silicon-based power amplifiers and RF front-end modules. The move is targeted at the IoT and 5G markets.

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